Unable to get Vivado ILA waveform captures from Arty A7 board

[josina]

I'm trying to use ILA to debug my design on Arty a7 board. However, I am not being able to get any waveform dump.

1) The ILA clock seems to be running. I routed this clock to one of the LEDs, and I see the LED is lit. Furthermore, when I turn off that clock via a switch (forcing the generating PLL to reset), and attempt an immediate trigger, I get "no clock is connected to this ILA" message which I don't get when the switch is flipped back on.

2) Design meets timings

3) Vivado's interaction with the FPGA via USB seems to be fine at least for loading the design, and USB-UART. I have a UART transceiver in the design which I have tested already and it seems to be working as expected.

4) I am using Vivado 2018.3 on an Ubuntu 16.04 machine.

When I click the immediate trigger, the ILA stays in the "Idle" state.

Can someone please tell me what I am missing, or guide me on how to continue my debug? Could it be that the ILA is actually getting a capture in the FPGA, but the capture somehow never makes it to Vivado through JTAG-USB?

[zygot]

3 minutes ago, josina said:

When I click the immediate trigger, the ILA stays in the "Idle" state.

Are there any messages from the Vivado Hardware Manager that you aren't telling us about or failed to notice?

When you try to trigger an unconditional capture are you sure that there was no activity? No redrawing of the waveform window?

[zygot]

8 minutes ago, josina said:

Furthermore, when I turn off that clock via a switch (forcing the generating PLL to reset)

Don't do that.

[josina]

No message. Below is what the Tcl Console in Vivado prints after a click for an immediate  trigger. 

run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7a100t_0] -filter {CELL_NAME=~"u_ila"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2020-May-10 09:19:13

 

I understand the ILA needs a free running clock. I turned off the clock to check if the behavior is different from when the clock is presumably on.

[zygot]

22 minutes ago, josina said:

turned off the clock to check if the behavior is different from when the clock is presumably on

I like the idea of having some indicator if my clocks are active. A better approach might be to have a free-running 26-bit, depending on the clock frequency,  counter and use the msb as an LED indicator.

It certainly seems that the Hardware Manager has no trouble finding the ILA debug core. You are saying that the signals added to the waveform window don't get re-drawn after an immediate trigger? Are your ILA signals in the clock domain that clocks the ILA? Is your ILA clock a 'real clock' and not logic derived? I realize that these sound like stupid questions but I don't recall ever seeing what I think that your are describing. At the moment you have me stumped.

When confounded by results that don't make sense I try a different approach as a sanity check. Usually this means bringing key signals out to a header and looking at them with a scope. If you don't have a scope you might have to be clever in figuring out a way to make the presence of high speed signals visible to a slow speed indicator like an LED.

 

[josina]

Thank you @zygot for the help. I think I am now able to solve the issue. The problem was that my JTAG speed was too fast, 15MHz - comparable to my ILA clock speed which is 20 MHz.

 

I reduced the JTAG speed to 1MHz, and now ILA is dumping captures.

 

Steps I followed to solve this are;

1) To know JTAG speed, I run the TCL command,

get_property PARAM.FREQUENCY [get_hw_targets */xilinx_tcf/Digilent/210319AD29CBA]  

This returned 15000000.

You can get the target name (*/xilinx_tcf/Digilent/210319AD29CBA) listed under "localhost" in  "Hardware" window. 

 

2) To set the JTAG speed to 1000000

set_property PARAM.FREQUENCY 1000000 [get_hw_targets */xilinx_tcf/Digilent/210319AD29CBA]

 

 

[zygot]

@josina, Thanks for posting your solution.