Add VHDL module to HDMI Demo Block Diagram?

[aadgl]

Hello,

I am using this project:
> Zybo Z7-20 HDMI Input/Output Demo Vivado 2018.2

It installs and runs nicely from the SDK per the documentation.  I have only tested the HDMI output function.  I am trying to add a VHDL module to the Block Diagram, something I have done on other Vivado projects.

I added the VHDL module to sources, enabled the btn, led5, led6, I/O in constraint .xdc, etc, and then added the VHDL module to the Block Diagram.  Vivado built the .bit file, transferred it to the SDK, uploaded .bit, and ran C code as usual.  I have used the same VHDL module in other Vivado projects and has always dropped in the Block Diagram and worked.

The VHDL module should flash led5_g, but nothing happens.  The Vivado messages indicate the the btn, led5, and led6 are not being used - yet they appear on the block diagram as being connected to the VHDL module.  Vivado did detect the VHDL module in the block diagram and automoation connected it to the correct PS7 clock.

Although the VHDL module appears to be part of the block diagram it doesn't appear to be incorporated into the .bit file.

Question - How can I integrate a VHDL module into the above demo project?

Thanks,
Dave

 

Added later - Below is a screenshot showing the original project with an added VHDL Module (two buttons and two leds):
(a) Simple module that has two buttons drive two leds (attached_
(b) Same module in block diagram with I/O ports
(c) .XDC file with I/O ports enabled (attached)
(d) Vivado reporting I/O ports not used

The same module, similarly embedded in a block diagram, runs as expected in a standalone Vivado 2018.2 project.

Zybo-Z7-Master.xdc btnled.vhd

[Ana-Maria Balas]

Hello @aadgl,

I think this is a bug of Vivado. If you right click on the design_1_i and select View Instantiation Template do you see these lines in the module:

  input [1:0]btn;
  output led5_g;
  output led6_g;

This happens very often in Vivado, if you have a lot of IPs in the block design and you add another module, the ports names are not updated in the instantiation module of the block design, and in implementation, the assigned port names from the constrain file are not found.

To resolve this issue right click on the design_1_i select Reset Output Products, then Generate Output products and then regenerate the bitstream file.

Also you should Validate the design every time you add a new module.

[aadgl]

Hi Ana-Maria,

Thanks for the reply and instructions on seeing more of Vivado's internal files.
I do see the three lines and I run Validate frequently.

Elsewhere I saw vague mention of the reset and generate steps, thanks for the detailed description of where to find them.

I did the reset, generate, and regenerate steps - same result, must be something else sideways in my setup.

Yesterday I found a work-around that appears to work (more details if anyone is interested):
> Extract the design_1_bd.tcl file and vivado-library folder from the project
> Create a new project
> Point the IP to the vivado_library folder
> Run the .TCL file
That recreated the project in such a way that I can add VHDL modules to it.

When I can, I will take another pass at correcting the Vivado Bug from a fresh install.

Also this Critical Warning keeps appearing:
> [IP_Flow 19-4965] IP ila_pixclk was packaged with board value 'digilentinc.com:nexys_video:part0:1.1'. Current project's board value is 'digilentinc.com:zybo-z7-20:part0:1.0'. Please update the project settings to match the packaged IP.
I am thinking the Zybo project has a Nexys IP module, to avoid the (likely) extraneous warning I renamed the Nexys board value.

Thanks again for your help,
Dave

 

[Ana-Maria Balas]

That critical warning doesn't affect your project. Nexys Video board was used when the IP was created and tested, but if doesn't affect the project.

I'm glad that you find a way to make the project to work, but what do you mean

Quote

Point the IP to the vivado_library folder

So after exporting the block design and importing it into new project and added the RTL module to the design, the buttons light the leds?

 

[aadgl]

Hi Ana-Maria,

I agree the Critical Warning doesn't affect the project, - pops-up a window that needs to be cleared, explained to others, etc - easier to edit the IP and avoid the pop-up.

Your question:
> Point the IP to the vivado_library folder
Reword - Point the project IP folder to the Demo project vivado_library folder

When rebuilding the project from "design_1_bd.tcl", it needs IP from this Demo project folder:
(a) <demo folder>\vivado_proj\Zybo-Z7-20-HDMI.ipdefs\repo_0\vivado-library
      Copy that "vivado-library" folder to a location for the new project
(b) Point the new project to that IP folder, from Vivado:
      Tools - Settings - IP - Repository, then click "+" to select IP Repo folder location
      Then browse to the "vivado-library" folder from (a)
The project can then be recreated from the .tcl file.  When built, everything builds and runs as expected.

Then other VHDL modules can be added to the recreated project, the led's work, etc.  I have significant other IP now working with the recreated project, runs in FreeRTOS, etc.

Thanks,
Dave
 

[Ana-Maria Balas]

In the future, for other projects where you need IPs, the vivado-library folder with IPs for Pmods and others is found here https://github.com/Digilent/vivado-library

It's great that you solve the problem. Sometimes myself I had to recreate new Vivado projects, because of some bugs and the method you found, exporting the block design, is the one that worked many times.

 

[aadgl]

Follow-up.  The project works well in Vivado 2019.1 for HDMI Output. I don't need HDMI Input, but decided to test anyway.  The v2019.1 does not appear to work for HDMI Input.  Oh well, a good project to work from, thanks.