AD2 Pattern Generator creates clock drift

[Pachelebel]

Hello,

I'm trying to use the AD2 pattern generator to create a (digital) sine wave using a value table table. I connected the external trigger to a clock of 10MHz, to create a sine with the frequency of 10/1024 MHz (with 1024 being the size of the table). When I compare the resulting sine wave to a sine wave generated by an FPGA, using a look-up  table with the same size and clock, I see that both signals drift apart from each other, even though both of them seem to have the same period. Am I using this tool the wrong way? Is my setting for a trigger wrong somehow? 

[attila]

Hi @Pachelebel

The drift is because the two systems use different oscillators. The precision of these is measured in parts-per-million. In long run these minor differences accumulate and resulting signals drift from each other, like clocks can be in hurry or late.
In higher frequency analysis you may also notice jitter.

1. As solution you can use periodic resynchronization.
Add delay for the FPGA logic between periods, this will leave time for the AD to resync in case the FPGA clock is faster.
Make the Patterns to have finite Run time, one period with Auto option. For each run the triggering will be repeated.

 

2. The best solution would be using the same clock.
Use another DIO output as clock and make you FPGA logic to use this as base clock, like here DIO-1
Use an enable/reset to asynchronously reset the logic, like here DIO-2,