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jsmithsrc

JTAG-SMT2-NC Power sequence

Question

Is there a way to prevent the JTAG-SMT2-NC USB pull-ups from activating (or delay activation)? When do the pullups become active?

To provide more background, I am designing a system where the FPGA will power up and configure prior to USB host. The USB connection will be "device down" -- no cable present. I have concern that the USB D+ pullup present on the JTAG-SMT2-NC (by USB spec requirements) may cause power on issues for the (unpowered) USB host.

Possible solutions I am considering:

  • Prevent pullup on USB D+ until USB Host is powered up.
    • I have a control signal to know when the USB host is powered up.
    • This may not be possible based on design of JTAG-SMT2
  • Power up JTAG-SMT2-NC only when USB host is powered up.
    • May cause issues at JTAG-SMT2-NC due to pullups present on JTAG signals in the FPGA applied when JTAG-SMT2-NC is not yet powered
    • Related: May Vref be powered prior to Vdd? (This way Vref is powered with FPGA configuration bank Vcco, and Vdd is powered up after USB host is powered).

Are there any allowable power up sequences for VDD/VREF that allow JTAG side of the device to power up without powering up the USB side until a later time?

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Hi jsmithsrc,

 

The USB controller has an option that can be enabled to prevent it from forcing current down the USB lines when VBUS isn't present. However, that option is not enabled on the SMT2 or SMT2-NC because it requires a resistor divider to connect VBUS to one of the IO pins. We are unable to enable this option because the IO pin required was utilized for the purposes of implementing 1149.7 (2-wire) support, due to the lack of any other suitable pins being available.

Originally the SMT2 and SMT2-NC were designed with the idea that VDD would power on prior to VREF or that they would ramp simultaneously. However, this sequence is not strictly required, as powering VREF prior to VDD does not backpower any of the components powered by VDD, nor does it violate any specifications of the components used to implement the design. I have confirmed that powering VREF prior to VDD does not cause any problems and that the SMT2/SMT2-NC is able to successfully program the JTAG device once VDD is powered.

Thanks,

Michael

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Hi jsmithsrc,

I personally don't know the answer to your question, but I have asked some of our applications engineers about this; they'll get back to you here on the forum.

Thanks,
JColvin

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