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Hello,

my name is Robert and I am a teacher (Professor) at the University of Applied Sciences and Arts in Hannover/Germany.

For the next semester I create a new lecture "Development of Digital Circuits" and I decided to emphasize and train the application of FPGAs and CPLDs. I'm just researching the different IDEs of several FPGA suppliers with the following requirements:

  • independence from PC operating system (I mostly use UBUNTU and Linux Mint, seldom W10)
  • free licenses to attract students to work at home with their own installation of the IDE
  • available low cost development boards (student budgets are small in Germany)
  • detailed documentation with background information and technical basics

Till now, only the Xilinx environment seems to meet all my requirements. So I installed Vitis 2020.1, bought an ARTY A7 and now I am here.

I think, I will make a lot of mistakes at the beginning and have to learn a lot. Beside this learning, I start to write a script for my students, so they hopefully get a usable description for programming their own devices.

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  • 1 month later...

Hello All,

I am Sridhar, getting into FPGAs and ASIC designs and Verilog since Feb 2020. Having some experiences in electronic hardware development, and now trying to add vlsi into my career.

Now been able to write RTL code, develop test bench in System Verilog, simulate in Vivado, can synthesize, implement and generate bit stream files.

Able to understand couple of errors and critical warnings, can solve them.

Now talking to my basys-3.

See you around the forum topics. Have a good day!

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  • 3 weeks later...
On 10/10/2020 at 9:13 AM, tt12345678 said:

My name is Tony. I'm a total beginner but am hoping eventually to be able to use a Zedboard to stream data from an AD7768 evaluation board to a PC.

Welcome to the world of FPGA development. The AD776x class of converters are pretty nifty for the right applications. I've done what you want to do for the AD7761 EVM, which is the AD7768 16-bit little brother, for the Nexys Video and Genesys2 boards. At the maximum 256 KS/s conversion rate across 8 channels for the 24-bit converter AD7768 this works out to about a 6 MB/s sustained streaming data rate.  Getting this to a PC will be a bit more challenging on the Zedboard as you'll need the Ethernet interface. ADI has some pretty good FPGA support for its evaluation boards but I wrote my own HDL. I suggest that you use the HDL design flow. The Zynq for a project like this just adds unnecessary complexity.

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