I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it?  I'm using Xilinx and the language  I used is VHDL. Here I attach a picture. Please help me.

Thank you.


Edited by Jaiko007

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8-1 multiplexers are generally quite simple, and the Xilinx synthesizer takes care of all the details for you.  When dealing with 5 inputs, the easy answer is to double some of the inputs so that you are still filling out an 8-1 multiplexer.

Of course, this depends upon what you are using your "clock" output for.  If you are using it to clock your FPGA, you might wish to use the Xilinx clocking primitives instead.  Such primitives make certain your output will be using the clocking resources of the chip.  If, instead, all of the "clocks" you are working with are gated against a much faster system clock, then the simple 8-1 multiplexer discussed above still works.

Hope this helps,


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