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Nexys A7-100T 8 digit 7 segment display.



I found a lot of open source and tutorials on how to build a 4 digit 7 segment display on the Nexys A7 board (or Nexys 4DDR). I was wondering how can I make all 8 digital displays light up and display a message in hexadecimals (ex: "85ECA921"). 

I'm doing this in xlinx vivado in VHDL code. I'll have attached of something that works for 4 digits, but can someone show me how to implement/ change the code to make all 8 digital displays work in that example I provided? 





serializer.xpr tb_serializer.vhd serializer.vhd my_genpulse.vhd hex2sevenseg.vhd serializer.xdc

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All the segments from any digit (0, 1, 2, 3) have common anode signal and individual cathode signals (CA, CB, ... , CG, DP). 

Accessing the segments of the Seven Segment Display is done for each individual digit (0, 1, 2, 3) by selecting its anode and setting the cathode signals (CA, CB, ... , CG, DP) for each segment according tot he information you want to display on that digit.

Cycling rapidly (faster than the eye can notice) between the 4 (n) display units creates the visual impression of all the digits being accessed simultaneously.

Please read more on this matter on   Seven-Segment Display chapter of the Nexys A7 reference manual.

Moving from 4 digits to 8 digits will require you to modify the way digits are cycled.

By looking into the serializer.vhd code you sent I can notice that this code is already prepared to deal with 8 digits, still only 4 are used (see how the Multiplexer is implemented on 3 bits).

Please try to understand how serializer.vhd is implemented.

Good luck.


Edited by Cristian.Fatu
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I'm sorry, I've looked over the manual many times. But I'm not really understanding how I can modify how digits are being cycled. Is it possible for me to see how the code in "serializer.vhd" is adjusted? 

Also does anything else gets adjusted or just the serialize.vhd? 

Would there then be four more states? S1, S2.....S7?


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Yes, you are right, although you are not confident.

That's the way to do it.

Add the missing states (S4 - S7), ensure proper transitions (Transitions process), ensure that Outputs proper selects the desired state (Outputs process), enlarge the dimension of signal s to 3  (2 downto 0), ensure proper segments selection for each state (what is now "2-to-4 decoder with active-low inputs" make it "3-to-4 decoder with active-low inputs".

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Additional to what @Cristian.Fatu said, maybe this tutorial will help you understand how the 7 segment is working: this is a detailed explanation https://www.fpga4student.com/2017/09/seven-segment-led-display-controller-basys3-fpga.html

and here is the vhdl code based on the explanation from above



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I fixed everything you have mentioned with the missing states and enlarged the dimensions. 

Quote: [ (what is now "2-to-4 decoder with active-low inputs" make it "3-to-4 decoder with active-low inputs".)]

How would I make/ program a 3-to-4 decoder? When I thought a decoder is a circuit with n inputs and 2^2 outputs. Do you mean make a 3-to-8 decoder? 

I have attached how I have changed my "serializer.vhd" code. How do I appraoch the 3-to-4 decoder? 

(I really appreciate everyone's help!) 



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1. First of all, there are 8  seven segment digit, so states are from S1 to S8. A state is when a digit is lit. One digit is lit at a time, but because the frequency is very high, the eye doesn't see that.

2. You also have to give values for the rest of the 4 digits, this is done with omux signal from the Multiplexer. I changed so that what is displayed on the first 4 digit to be same for the next 4 digit, but you can think of ideas to display whatever you want and change it

3. It's 3 to 8 decoder. Just think about: there are 8 seven segment digit (AN has 8 bit, one bit for each digit) and you select each digit at a time, so you have 8 states. To enable a digit you set the corresponding bit of the AN for that digit to low logic ("0"). If there are 8 states, then you need 3 bits to cover all the states.

4. The s signal is mapped for each state, so you have to change that in the Outputs process too


-- This VHDL file was developed by Daniel Llamocca (2013).  It may be
-- freely copied and/or distributed at no cost.  Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use.  Daniel Llamocca does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- accompany any copy of this file.

library IEEE;
use ieee.math_real.log2;
use ieee.math_real.ceil;

-- This file works for the Nexys-4 Board with eight 7-segment displays
entity serializer is
	port (resetn, clock: in std_logic; -- resetn: active-low input, pause: active-high input
	      A, B, C, D : in std_logic_vector (3 downto 0);
			segs: out std_logic_vector (6 downto 0); -- active-low input for all 7-segment displays
			AN: out std_logic_vector (7 downto 0)); -- eight active-low enable for each 7-segment display
end serializer;

architecture Behavioral of serializer is
	component my_genpulse
		generic (COUNT: INTEGER:= (10**8)/2); -- (10**8)/2 cycles of T = 10 ns --> 0.5 s
		port (clock, resetn, E: in std_logic;
				Q: out std_logic_vector ( integer(ceil(log2(real(COUNT)))) - 1 downto 0);
				z: out std_logic);
	end component;
	component hex2sevenseg
		port (hex: in std_logic_vector (3 downto 0);
				leds: out std_logic_vector (6 downto 0));
	end component;
	type state is (S1, S2, S3, S4, S5, S6, S7, S8);
	signal y: state;
	-- for the 3 bit to 8 bit decoder, s is the input signal of the decoder
	signal s: std_logic_vector (2 downto 0); 
	--omux selects the states for each value of the s
	signal omux: std_logic_vector (3 downto 0);
	signal E: std_logic;
	-- for the 3 bit to 8 bit decoder, ENt is the output signal of the decoder
	signal ENt: std_logic_vector (7 downto 0);
	signal leds: std_logic_vector (6 downto 0);

-- Counter: 0.001s
gz: my_genpulse generic map (COUNT => 10**5)
    port map (clock => clock, resetn => resetn, E => '1', z => E);

-- Multiplexor
with s select
	omux <= A when "000",
	        B when "001",
			C when "010",
			D when "011",
			A when "100",
			B when "101",
			C when "110",
			D when others;
seg7: hex2sevenseg port map (hex => omux, leds => leds);

segs <= not(leds);
-- 3-to-8 decoder with active-low inputs, '1' is inactive for active-low enable.
with s select
		ENt <=  "11111110" when "000",
			    "11111101" when "001",
			    "11111011" when "010",
			    "11110111" when "011",
			    "11101111" when "100",
			    "11011111" when "101",
			    "10111111" when "110",
			    "01111111" when others;

-- We have 8 7-segment displays.

	 AN <= ENt;
	Transitions: process (resetn, clock, E)
		if resetn = '0' then -- asynchronous signal
			y <= S1; -- if resetn asserted, go to initial state: S1			
		elsif (clock'event and clock = '1') then
				case y is
					when S1 => if E =  '1' then y <= S2; else y <= S1; end if;
					when S2 => if E =  '1' then y <= S3; else y <= S2; end if;
					when S3 => if E =  '1' then y <= S4; else y <= S3; end if;
					when S4 => if E =  '1' then y <= S5; else y <= S4; end if;
                    when S5 => if E =  '1' then y <= S6; else y <= S5; end if;
					when S6 => if E =  '1' then y <= S7; else y <= S6; end if;
					when S7 => if E =  '1' then y <= S8; else y <= S7; end if;
					when S8 => if E =  '1' then y <= S1; else y <= S8; end if;

				end case;
		end if;		
	end process;
	Outputs: process (y)
		case y is
			when S1 => s <= "000";
			when S2 => s <= "001";
			when S3 => s <= "010";
			when S4 => s <= "011";
			when S5 => s <= "100";
			when S6 => s <= "101";
			when S7 => s <= "110";
			when S8 => s <= "111";
		end case;
	end process;
end Behavioral;


Edited by Ana-Maria Balas
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