Zmod ADC differential Clock

[svaughn442]

Hi,

I have an Eclypse Z7 board with Zmod DAC and ADC. The DAC is working. I can not locate the correct protocol for the ADC differential clock driven by the FPGA in the Zmod H/W reference manual?

thanks

Stan

[zygot]

1 hour ago, svaughn442 said:

I can not locate the correct protocol for the ADC differential clock driven by the FPGA

The AD9648 differential clock is DIFF_SSTL18_I according to the ZMODADC_0_ZMODADC.xdc constraints file provided by Digilent. The data interface is nothing exotic, just single-ended parallel DDR. The clock has 100 ohm parallel termination on the ZMOD.

[svaughn442]

Hi ,

I have adjusted the clock differential. I am sending into Channel 1 ,  a gaussian wave , 1 usec wide. amplitude is 1.0V ( from the Zmod DAC).  I have the output of the low level component mapped into dual port RAM. I am also using the debug core and H/W manager to monitor the output of Ch1 of the low level component prior to the RAM input.  I can see the gaussian data going to the DAC with the H/W manager. And I am plotting the gaussian wave on the oscilloscope. I have enabled the GAIN and Coupling relays in the low level component. I can set the gain and coupling relays. I have tried both AC and DC coupling and have the high gain now set ( Ch1Gain = 1). I am still not receiving any output. I have a used the clocking wizard and the 100 MHz system clock  multiplied by 4 for the 400 MHz to drive the low level component ADC clock input.  Still not seeing any outputs from the Zmod ADC. Suggestions?

thanks

[zygot]

3 hours ago, svaughn442 said:

Still not seeing any outputs from the Zmod ADC. Suggestions?

I'm guessing here that you are 'rolling your own interface designs'  for the DAC and ADC ZMODS. You don't mention a serial interface to configure the ADC. At a minimum you have to set the AD9648 to output to the correct port as DAxx is not connected. The suggested output is to interleave both channels on DBxx. You've hopefully read through the datasheets for the devices on both ZMODs but this is my first thought.

When working with a new ADC I'd start off using one of the test wave-forms that are available so that I can at least check off data connectivity.

[svaughn442]

Hi,

I have adjusted the ADC differential clock protocol to DIFF_SSTL18_I . I am not receiving anything on CLKOUT_ADC. I would expect to see 100 MHz LVCMOS18 here.  what could stop this? 

[zygot]

20 minutes ago, svaughn442 said:

I am not receiving anything on CLKOUT_ADC.

You still haven't provided any information about how you configure the ADC registers, so I don't see the point in asking any other questions for now.

BTW the ZmodADC schematic AD9648 component doesn't match the datasheet. The Digilent ADC documentation doesn't match the source code.

Even if you decide to forego the current Digilent ZMOD IP I strongly suggest building and studying both the Standalone and Linux demo builds for insight into how the system is supposed to work. It's a mess, overly complicated,  and the documentation, at least for the ADC ZMOD AXI IP, isn't correct but the schematics, datasheets, and ZMOD documentation are valid. I'm still hoping that someone at Digilent takes charge and decides what the heck the Eclypse-Z7 is supposed to be and turns it into something that users can understand and will want to use without having to dedicate an engineering team to figure out what's there.

There are only a few similar inexpensive platforms. The excellent and well supported Analog Discovery product is a limited capability and closed 'instrument' product, at least in terms of capability. The Red Pitaya Stemlab 125-14 Starter Kit has similar, though more limited, capabilities compared to an Eclypse-Z7 with one DAC and one ADC ZMOD but is actually a successful and well supported Linux 'instrument' platform with the possibility of being user modified. Opal Kelly, where SYZYGY was born, seems to have moved onto something else as they haven't updated support for anything SYZYGY in quite a while now.

Building the Vivado hardware and exporting it to the SDK and building the Standalone or Linux demos should help pinpoint where you might have gone astray. All of the demos do work though it might take a while to figure out how to get there. At least it's a point of reference. 

[svaughn442]

thanks for the Info!  I am relying on the FSM in the low level component to initialize the ADC, I don t have the external SPI on the Zynq side connected. I think this will be perfect for our application for a high power RF instrument measuring detected RF waveforms. I have not enabled the external configuration registers ( the group of 18 bit registers) I have a general purpose AXI peripheral register bank configured to control these registers as well as gain and coupling ( which are enabled in the generics). I have just  connected the sInitDone signal to an LED so I can verify if the FSM is completing. I could also use chipscope to look at the SPI traffic. 

[zygot]

1 hour ago, svaughn442 said:

I am relying on the FSM in the low level component to initialize the ADC

I assume that what you mean is that you are using the AD9648_SPI.vhd source in conjunction with your own AXI blocks to initialize the ADC. The AD9648_SPI component provided by Digilent is intended to connect the ADC AXI IP to the AD9648 pins so that the processor can do the initialization. By itself, AD9648_SPI.vhd doesn't do much. It would be easier to troubleshoot if your code was able to read registers as well as write them. As I've mentioned before a good way to see if you can initialize the converter is to put it into a mode that outputs a known test waveform.

Debugging and verifying the ADC initialization process is certainly a good starting point.

[svaughn442]

Hi, the generics in the LL component VHDL code had the external register values set to true for debug , which in my register controller were all set to 0. I disabled so that the internal static register values were used. Once I did this I began receiving data! Looks good! thanks again for your support, keeps me looking

[zygot]

Doh! (head slap) Been there, done that.. Thanks for the resolution confirmation.