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PModCLP design flaw?


juergenR

Question

Hi, these days I found a PModCLP I purchased some years ago and decided to reimplement the control for it.

In particular, I decided to operate the module in a differnt manner:

  • use the 4 bit mode to spare some lines
  • read status bit to know when a command has been finished

As a consequence, there is bidirectional data transfer on the data bus including High-Z phases and DB0 to DB3 will be left unconnected on the hardware.

When measuring DB7 to see the status, I got quite surprised because I measured up to 4.8V on the data line - far beyond the PMod specs! When looking at the schematics (RevB), I see this VTerm2.5 stuff which I guess should limit the voltage on the 3.3V inputs. But I don't understand how this can work: as soon as an open DB pin exceeds 2.5V + 0.7V = 3.2V current will flow back to IC1, increasing voltage at that output. The regulator will shut down and the whole VTerm potential will mount, affecting also the other outputs. Actually I measure 4.6 at C1 when grounding DB0 to DB3, a bit more when leaving all DBs open.

As I understand it, this circuit will only protect outputs but not inputs. Am I right or do I miss someting?

BTW, measuring the current to ground on a DB pin gives me about 2.5mA, and a total of 18mA for all 8 pins. This is too high compared to what the KS0066U datasheet states. Does anybody have other measurements?

Thanks for any comments, Jürgen

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I used an Arty Z7-20 board, using PModA connector. Power supply via USB, nothing else connected.

The connection to the PModCLP was like this (Z7-20 --> CLP): Pins 1..4 --> DB4-7, Pins 7..10 --> Control signals. DB0..3 left open. Used a cable I bought also together with the CLP.

Hope this helps,

Jürgen

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Hi @juergenR,

We looked into this some more and while none of us had at Pmod CLP with us at home to do any direct measurements, it does seem that there is a design flaw as the IC1 does not seem to be able to sink much current so excess current isn't flowing through the diodes D1-D4 as intended. This combined with the fact that the Arty Z7 boards do not have any current limiting resistors on their Pmod ports (unlike the vast majority of Digilent boards did in the 8 or so years between the Pmod CLP being developed and the Arty Z7 getting developed) so the current and voltage may be too high for the FPGA IO pins.

At this point, I would recommend not using the Pmod CLP as is with the Arty Z7-20 (or at least use caution) because if the measurements you are getting are correct, there is a chance of damaging the pin or the IO bank on the FPGA. Ideally, if the voltage is getting dropped down from 5V from the Pmod CLP to 3.3V on the Pmod port on the FPGA, the one 200 Ohm series resistor would give a current of 8.5 mA, which should be okay, but is rather high considering the maximum input current through the clamp diode on a Z7-20 chip is 10 mA (table 2 of DS187). An extra 200 Ohm resistor in series would help make this amount of current flow safer, so the current plan as I understand it on Digilent's end is to more formally review this part on our end and make a change.

Edit: I did note that the Arduino styled headers on the Arty Z7-20 do have this extra 200 Ohm resistor, so it may be worth pursuing to connect through those headers instead

Let me know if you have any questions.

Thank you,
JColvin

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Thanks for your answer and suggestions. I am happy you got my point. For the Arty-Z7 board: actually those pins seem to work still as intended and I will follow your proposals. ?

BTW, I still believe that the current flow out of the CLP is unusal high and I am not sure if my CLP has a damage elsewhere. Maybe it is worth to check the nominal current flows in and out of the controller - unfortunately I don't have reliable information about them.

Best regards,

Jürgen

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