Question

I am having layers of problems with the Pmod MicroSD.  My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. 

Issues:

  1. [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7]      I get this error for 4 pins     

    set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t]
    set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t]
    set_property BOARD_PIN {JB9} [get_ports Pmod_out_pin9_t]
    set_property BOARD_PIN {JB10} [get_ports Pmod_out_pin10_t] 

     Vivado does finish making the bitstream.                                                                                                                                                                                              

  2. I then push on incase it works anyway.  In the SDK I get another error.
    12:28:33 **** Incremental Build of configuration Debug for project uSD ****
    make all 
    'Building target: uSD.elf'
    'Invoking: MicroBlaze g++ linker'
    mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf"  ./src/main.o   -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group
    c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem'
    c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 159832 bytes
    collect2.exe: error: ld returned 1 exit status
    make: *** [uSD.elf] Error 1
    
    12:28:35 Build Finished (took 1s.389ms)

    Without really knowing what I'm doing, I read the error and think I need to allocate more local memory to the microblaze. "overflowed by 159832 bytes"   I then open up my block design and try to customize the microblaze but see no place in change the memory it is allocated.  I used the address editor and increase the allocated memory for the dlmb to 128K and then the ilmb to 128K. If I try 256K for each the validation fails. Then after this I get a slightly better SDK error.

    13:13:22 **** Auto Build of configuration Debug for project uSD ****
    make all 
    'Building file: ../src/main.cc'
    'Invoking: MicroBlaze g++ compiler'
    mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -I../../uSD_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cc"
    'Finished building: ../src/main.cc'
    ' '
    'Building target: uSD.elf'
    'Invoking: MicroBlaze g++ linker'
    mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf"  ./src/main.o   -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group
    c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem'
    c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 61528 bytes
    collect2.exe: error: ld returned 1 exit status
    make: *** [uSD.elf] Error 1
    
    13:13:25 Build Finished (took 2s.724ms)

    My over flow is down to 61528 bytes.

I am doing all this by following the IPI tutorial and just adding the PmodSD to it. here and  here

 

Thanks

FBOARC

PS

I am using Vivado 2018.2 as that is the version in the tutorial.

 

 

Edited by FlyingBlindOnARocketCycle
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Hi @FlyingBlindOnARocketCycle,

Which YouTube tutorial are you referring to? There is a Pmod WiFi tutorial from Digilent that shows using the Pmod WiFi for the Arty (https://www.youtube.com/watch?v=KTeTMv3oiPw) but that uses Vivado 2016.2, though we have confirmed that the project works in newer versions of Vivado.

I see that you are following our guides for both Pmod IPs and the Getting Started with Vivado IPI, which was what I was going to recommend. I just ran through the bitstream creation for the Pmod SD with a Basys 3 in Vivado 2018.2 and did not have to do anything to change .xdc values. Do you know which release of the Digilent Vivado Library (https://github.com/Digilent/vivado-library/releases) you are using? I don't believe there have any been recent changes.

With regards to the SDK errors you encountered, it turns out that the Pmod SD drivers in combination with the bitstream (even if you compress the bitstream) are too large to fit within the BRAM present on the Basys 3. The byte overflow values add up. With the default 32 KB allocated, you overflowed by 159832 bytes. When you upped the allocation to 128 KB (96 KB increase) the overflow went down to approximately 61528 bytes (the math doesn't quite work, so I presume there is some more memory usage when configuring Microblaze for extra memory. The reason 256 KB didn't work is because the Basys 3 only has 1800 Kbits of BRAM (225 KB).

TL;DR, to get the Pmod SD to work on the Basys 3, you will need a SPI bootloader application for the SDK project as described in our tutorial here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start.

Let me know if you have any questions.

Thanks,
JColvin

 

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Posted (edited)

Hi @JColvin

Thank you for taking the time to create a bitstream for the Pmod SD. 

Are you saying that when you did this in  "Vivado 2018.2 and did not have to do anything to change .xdc values"  that you created a bitstream with no errors?  When I try in vivado 2018.2, it does create a bitstream as I mentioned but I also get errors.  I am using the 2018.2-1 rev of the Digilent IP library.  Also I should mention that I have Vivado project settings to default to VHDL as opposed to Verilog.  Would that make a difference at all?  I am comfortable in VHDL and struggle in Verilog so I like it when Vivado makes the top wrapper for me in VHDL.

Quote

it turns out that the Pmod SD drivers in combination with the bitstream (even if you compress the bitstream) are too large to fit within the BRAM present on the Basys 3.

The above statement is very unfortunate for me. When the youtube states at the beginning "if you don't have the arty you can also use any of our artix 7 fpga boards..."  I believed I had acquired all the hardware I needed to implement this project.  I'm trying to use this as a learning experience and it seems to be throwing up road blocks.  At the end of the day I don't really care about the SD Pmod I bought as I only bought it because I was lead to believe it was required to use the Wifi Pmod in accordance with the tutorial video.

With only a fingertip hold of what I'm doing here, I fear the alternative paths I need to follow like "a SPI bootloader application for the SDK project" are going to lead to endless frustration. Until attempting this project I had never opened the SDK.  The tutorial says

Quote

Before you start; this guide assumes that you already have a Microblaze system built complete with Quad SPI, External Memory, and Uart cores,...

External memory?  The Basys3 has none. What does it mean when referencing the SPI flash. I have used SPI flash to load a design file (MCS) but I have never had to implemented it as part of my design. I always had vivado build the file in the "Generate Memory Configuration File" window.

Please advise further.

By the way, the video uses an Arty. There are two version of the Arty. I wonder if the Arty version with the 35T chip would be equally incapable as the Basys3? 

Edited by FlyingBlindOnARocketCycle
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Posted (edited)

Hey @JColvin

Do you think you could post your Basys3 project with the functional Pmod SD?  Then I could sift through and see what I'm doing different/wrong.  Maybe a block design tcl?  I attached my latest attempt.  It was done in Vivado 2018.2 with the latest Digilent library (2019_1)

Thanks

FBOARC

Edit: Well hang on to your flipflops darn it! When I rebuild this project, from my OWN stinking project tcl, it builds with different warnings and does not spit out the "BOARD_PART_PIN cannot be assigned to more than one port" errors that I get when I create the project originally.

I get this

[filemgmt 20-1673] Unlinking is not permitted for the source file: 'H:/microSD/microSD.srcs/sources_1/bd/uSD_bd/uSD_bd.bd'

and I get the "critical" warnings this IP was packaged for a different board blah blah blah.

I see the IP design out-of-contect Module Runs all say they are using cached IP results which I don't understand a I started the build from the tcl as a brand new project.  I do think this altered behavior is a clue.  I don't know what to do with this clue....

uSD.tcl

Edited by FlyingBlindOnARocketCycle
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Hi @FlyingBlindOnARocketCycle,

The video I referenced uses the Arty-35T (same chip as the Basys 3). It gets away with using the WiFi chip and SD card though because it has external memory (in this case DDR3) already built into the board. I was also using Vivado 2018.2 with the latest Digilent Vivado library 2019_1.

Quote

Also I should mention that I have Vivado project settings to default to VHDL as opposed to Verilog.  Would that make a difference at all?  I am comfortable in VHDL and struggle in Verilog so I like it when Vivado makes the top wrapper for me in VHDL.

I don't believe that should make a difference. I recreated the base project (without the proper support for necessary bootloading procedures) and have attached their both of their tcl scripts for the block diagram.

The SD card is needed if you want to use the html files that we provide so that you can run the HTTP server demo as it pulls the files from the SD card and hosts via the server running on the host board and WiFi chip. If you are instead just wanting the board to be a TCP client to communicate with a server running somewhere else.

You are right about the need of external memory being a red flag for the Basys 3; I didn't consider that when I posted after work hours last Friday. I will need to see if I can get the SPI flash project and bootloader both stored nicely in the flash memory, though getting an SREC bootloader to work correctly is a bit of a chore, so we may end up using an MCS file instead. I will let you know what I find.

Thanks,
JColvin

design_1VHDL.tcl design_1Verilog.tcl

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