When Hs3 is plugged in, fpga fails to set done high

[frankZ]

Running a K7 on our own PCB and having issues with the Done output not going high on powerup unless I remove the HS3 and cycle power. I've checked the Boot Status and Config Status in the Hardware Device Properties box and boot_Status.Bit00_0_status_valid is 0 and Bit13 and 14 in the Config_status are both low (Done Internal and Done pin).

I'm running 66MHz CClk, with SpiX4 on a Spansion s25FL512s-spi-x1_x2_x4.

[JColvin]

Hi @frankZ,

I apologize for the delay.

I have a couple of clarification questions since I'm a little confused about your setup. Are you using the JTAG HS3 to configure the Kintex 7 chip or you programming the Spansion chip?

From your description, it sounds like you are attempting to boot-up from SPI flash, but are unable to do so while the HS3 is connected to your board; is that accurate?

Thanks,
JColvin

[frankZ]

I'm just turning on power and waiting on done to go high after reading the flash. The HS3 should be idle.There's an MCU monitoring the Done line to verify the FPGA exists and is ready to program.

[JColvin]

Hi @frankZ,

I asked another engineer about this and we're not certain what the issue might be at the moment since SPI configuration is outside of the scan chain on a Kintex-7. I presume that is also the case on your setup? Otherwise, if Vivado, Digilent's Adept, or other Xilinx is connected to the HS3, it could be left open and have active buffers driving the lines.

I also presume that your SPI flash is set up in master mode rather than a slave mode? Again, this might not matter with the Kintex-7 setup, but we're looking for some clues as to what might be happening, so if you happen to think of anything unique or different about your configuration/programming setup on your board, that could help.

Thanks,
JColvin

[frankZ]

The flash is shown in the image, the alternate flash is not installed. It's bin file is setup for x4 but not sure where that gets configured into the fpga. The software is Vivado 17.2 Lab Edition. 

Is it possible the HS3 is overdriving the mode pins internally and forcing JTag mode?

 

[JColvin]

Hi @frankZ,

We don't see anything specifically wrong with your setup. What the other engineer recommend to try is as follows:

Probe the +3.3V across a power cycle to see if it actually goes down all the way to 0 or if there is some back powering through the FPGA clamp diodes. The JTAG HS3 buffers will be in tri-state under two scenarios :

1. device isn't open in Adept or Vivado/Xilinx tool
2. pin 2 of the JTAG header as at 0V

If the JTAG signals don't end up tri-stated then they can drive current through the clamp diodes of the FPGA when 3.3V is off and then when the switch gets flipped on the FPGA may not have a clean reset, which could potentially lead to what you are experiencing currently.

Let us know what you find.

Thanks,
JColvin

[frankZ]

Figures, hook up  the meter and now I can't get it to fail. See if the problem returns some day.

[frankZ]

Turns out if the hardware manager is running and connected, the tck is constantly running.

I typically use the lab edition as a separate debugger since it remembers the ila configuration.

[frankZ]

Is there a driver fix to disable the outputs till actually needed? Appears if TCK is active during boot, I never get a done.

As is I need to unplug the HS3 to boot then plug back in hot. I've seen hardware manager go off in the weeds trying to "Close" the hardware, possibly from plugging in non-monotonically.

[asmi]

Can you try adding weak pullup resistors (10K) to TCK and TMS lines as recommended by the spec? I actually have pullups for all 4 JTAG signals on my designs, and I never had an issue you're describing.