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ARTY MicroBlaze Running at 100MHz


digitalone

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Hi digitalone,

I apologize for not getting back to you sooner. I'm not sure if those rates are limited internally by Artix7 architecture or by MIG (I've seen some evidence for both). I'll ask some of our applications engineers about this; they'll get back to you here on the forum.

Thanks,
JColvin

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Hi digitalone,

Yes you can run the Microblaze at 100MHz. I can't say for sure how well it will work at faster clocks though.

You can generate this clock from the clocking wizard, just make sure you clock M00_ACLK on the memory interconnect with the 83.3MHz clock. Our tutorial used to do it this way, but we were failing timing, although I just tried it out myself and it worked just fine. I'll have to go back and change that back.

You can also generate this clock from the MIG. To do this, double click the MIG IP and click "Next" until you see "Select additional clocks" and check that box. Choose your clock and then click "Next","Next","Next","Next", "Validate", "OK", "Next","Next","Next", "Accept","Next","Next","Generate".

It's a bit of a pain, but you'll get an output clock of close to 100MHz.

The DDR3 is clocked as fast as it can be.

Hope this helps!

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I have a Spartan-6 design based on the SP605 board using a larger FPGA of course.

It is running the Microblaze at 100MHz and has 128MB of DDR3 memory.  I think the memory bus there is running at the same 100MHz as the Microblaze, but the Spartan-6 memory interface seems to be different than the Artix-7's and I am not that familiar with the Artix-7 yet.

Would I just need a higher speed grade version of the DDR3 memory the ARTY uses to allow it to run at the full 100Mhz?

I would like to run all my designs at 100Mhz at a minimum, 200Mhz would be even better going forward, but I am not sure if that is possible.

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Hi digitalone,

The DDR3 on the Arty is actually running much faster, at about 667Mhz, it is just parallel data sampled at a slower rate. I'm pretty sure the memory interconnect samples 128bits of data at 83.3Mhz (the data bus is 16 bits wide). I'm not entirely sure, but in theory you might be able to clock the DDR3 slower to make the ui_clk run at 100Mhz, but you'd be losing a lot of performance, and I think there is a small bug in the MIG that doesn't allow this.

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On my Spartan-6 design a 200MHz clock comes in off the board and creates the 100Mhz for the Microblaze and two different phase 600MHz for the DDR3.  The Artix-7 to DDR3 seems very different like some things (like 600Mhz) are hidden.  Maybe they are generated by the PHY layer going out to the DDR3 for Artix-7?

Above you said " just make sure you clock M00_ACLK on the memory interconnect with the 83.3MHz clock "

So if I clock the Microblaze at 100MHz and the DDR3 interface is clocked at 83.3Mhz isn't that slowing things down jumping across clock domains on the AXI interface?

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From what I understand, I think the Spartan-6 series FPGAs included the memory interface, and you only neded to create a wrapper for it to work. The Artix-7 has more generic components which allows the FPGA to interface with many more types of memory if needed. This means Xilinx created a MIG to implement this in hardware. You can see all of the internal clocks the MIG uses in the Summary page if you double click the MIG block in your design.

As for your second question, yes there will be a bit of latency in crossing the clock domains, but you are still getting almost exactly the same performance. You can find all of the nitty-gritty details in the 7-Series MIG User Guide, but I'm sure that you are getting the best performance possible as it is.

Don't forget, you can also enable caching in the Microblaze!

I hope this helps!

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