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ISSUES IN FILTER IMPLEMENTATION IN VIVADO BLOCK DESIGN


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Dear Sir,

I am trying to implement fir compiler in vivado block design. I have generated two frequencies , 200Khz and 1Mhz using DDS Compiler. I designed a Low Pass Filter Using FDATool in Matlab (figure attached). I am analyzing waveform using ILA but FIR Compiler output is either a straight DC or an irregular signal. I have attached Screenshots of block design, filter design and waveform.

Your kind response will be highly appreciated.

 

blockdesign.PNG

filterdesign.PNG

waveform.PNG

Edited by RJ16
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@Dan Sir the output is still not as required. (Figure1)

Also Can you please tell me whether my block design is correct or not. Actually I am confused between using Adder or Multiplier. I have tried both ways.

 

wave2.PNG

Edited by RJ16
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@RJ16,

One other question ... on your filter design page, why is the sample rate set at 48kHz, if you are going to be placing a 1MHz signal into the design?  I would note that you've ignored the TREADY signals, so any filter you might've built that depends upon a slower sample rate of the input could clearly be expected to produce junk at the output.

The rule is, if ever TVALID && !TREADY, then TVALID must stay high and TDATA cannot be allowed to change.

Filters that run at the full FPGA's rate, say at about 100MHz or above. can be expected to use one multiply per filter coefficient.  If you go that road, you'll also need to double check that your FPGA has enough multiply elements to support such a filter.

Dan

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@RJ16,

... and how does that sampling rate compare to your system clock rate?  That is, the clock rate that's running all of this logic?  10MHz seems kind of low.

I think we can both agree at this point that the test you are providing this filter with is leaving you confused.  Let me suggest a different test.  Why not run an impulse into the system?  The result should look *exactly* like the filter coefficients you fed it with.  Any deviation should point you directly at what's going right or wrong with the filter.  Debugging from there might involve only setting one or two coefficients and leaving the rest at zero, and then applying an impulse to the filter again.

Practically, the two biggest problems most folks have with these things is not the filter itself, but rather the data display, the handshaking, and figuring out how to simulate things properly.  The output of your addsub suggests a display problem.  The 48kHz, and now 10MHz clock rate, suggests a handshaking problem.  Not being able to dig into the system to see what's happening and how to fix it is another issue.  Other filters don't have that problem.

Dan

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