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Genesys 2 RAM modules not included in master XDC

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Hello, I may be seeing something incorrectly, but there are 1GB worth of RAM chips on the Genesys 2 board. The RAM is not included on the master XDC file. Is this a mistake, or is the ram coupled on a deeper level to where the XDC does not need to specify it?

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Hey @asmi,

Thanks for notifying us on this. While the settings before worked, they weren't optimal. I've changed the mig.prj in the Genesys2 board file to your recommendations. I'm not sure why VccAuxIO was set to 1.8V, the setting is not changeable in the MIG and must default to that value. Either way it's fixed now.



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8 hours ago, JColvin said:

Hi @tuskiomi,

For reference, you can see what settings Digilent applied for the Genesys 2 DDR in it's mig.prj here: https://github.com/Digilent/vivado-boards/blob/master/new/board_files/genesys2/H/mig.prj.


Those settings are incorrect BTW. Specifically, this file has VccAuxIO of 1.8 V while in reality it's 2.0 V, the clock period is also only 2500 ps (or 400 MHz), the board's user guide recommends 1112 ps (899.28 MHz). Clock period of 1111 ps (900.09 MHz) works best in practice though, because it allows setting input clock to exactly 200 MHz, which is what's present on the board. I get that this board is designed for people who know their way around schematics, but still - I think both MIG project file and the user guide needs to be updated. I know that we're talking about only 1 picosecond of difference, and IODELAYCTRL technically allows tolerance of ±10 MHz, but I prefer having exact values as it makes calculations easier if you use delay blocks in your custom logic elsewhere.

Edited by asmi
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