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Running the application project on multi-core ARM processor on ZYNQ MPSoc


fpga_123

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Hello,

I would like to share the steps for working with two or more ARM Cortex processors on FPGA from SDK at the same time. I have been using CORE 0 and CORE 1 from the four 64-bit ARM cores available. The FPGA board that I am using is : Zynq UltraScale+ ZCU102-ES2 Evaluation Board (xczu9eg-ffvb1156-2-i-es2) from Xilinx. We start with the block design creation in Vivado Design Suite. This does not include any custom generated HLS IP. The block design contains the Zynq Ultrascale+ PS IP available in the Vivado IP catalog.

The following steps can help you in making this project work :

1. Apply the "Reset Block Automation", once the IP is available in the block design window. Double click on it to change the configurations. I am using the 32 GB of DDR4 memory so the DDR configuration have been set accordingly. You can refer the ddr_config.png and ddr_config1.png images attached.

2. Remaining configurations remain the same. Connect the pl_clk0 port to maxihpm0_fpd_aclk on the Zynq PS IP. 

3. Create the HDL Wrapper, Run the Synthesis, Implementation and Generate the Bit stream.

4. Export the Hardware into SDK and then create the two application projects as follows. Create the first application project for hello world. Name it say "core_0_hw". Please select the Processor as psu_cortex53_0 in the dialog box. Select the hello world template and create the application project. Under the source folder, helloworld.c can be modified to have any print statement or a series of statements.

5. Create the second application project say "core_1_hw" and select the processor as psu_cortex53_1 in the dialog box. Select the hello world template and create the application project.You can keep a different print statement here w.r.t to first application project to recognize the difference in the SDK terminal when running the project.

SOMETHING IMPORTANT : The linker script decides where to place the program code in the memory, here it is DDR. Under the source tab, double click on the file "lscript.ld".  The file will open in editor window. It should look something like the one in linkerscript.png file attached. The code is placed in the psu_ddr_0_MEM_0. Since both the cores share the same DDR, it is not possible to load both the project codes at same starting address. We need to change these addresses in the linker script of both the projects. The DDR4 range available in this case is : 0x00000000 - 0x7FFFFFFF. So, I allocated the range 0x00000000 - 0x3FFFFFFF to the linker script for first application project and 0X40000000 - 0X7FFFFFFF to the linker script for second application project.

The changes to Base Addresses can be made directly by double clicking on the value and overwriting the new address value. You can save it using Ctrl+S.

6. Once both the projects are ready, under the "Run" tab, select Run configurations. Select the Xilinx System Debugger to run these projects. If you have exported the bit stream with the hardware platform, you will be able to program the FPGA from SDK itself. Check the boxes as shown in the image file run_config.png. Then under the application tab, select the parameters as shown in the image file app_tab.png. Once this is done, click the Run tab.

7. Make sure that FPGA board is ON and the COM port is connect properly. (Baud rate : 115200)

8. You can also open the XSCT console to monitor the status of the core. It may show like this when the applications are running on both core.

Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #1 (target 10) Running

9. The SDK terminal should display the messages now.

 

Hope this helps.

Shyama Gandhi,

ddr_config.PNG

ddr_config1.PNG

app_tab.PNG

run_config.PNG

linkerscrpit.PNG

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