how to use ipcore for uart for echo

[Vishnuk]

Hi,

can somebody tell me how to use uart ipcore uisng vivado, basys 3 board. i want to configure the uart core for echo purpose can someone tell me how to do it. what are the steps ?

[D@n]

@Vishnuk,

You asked a very similar question not that long ago.  Would you care to share why that question didn't answer what you were looking for today, or what you learned from that exercise that didn't get you as far as you want to today?

It might help us focus the discussion now on what you are actually looking for and struggling with.

Dan

[Vishnuk]

hi,

i went through the pdf files on ipcore as suggested but, they haven t mentioned as to how to configure in vhdl. i was able to design the block diagram, generate hdl wrapper, but cannot modify it for my use. i want to know as to how do i modify the ipc ore for my use, after creating hdl wrapper.

[Vishnuk]

hi, below i have attached the block diagram image for uart ip core. can somebody tell me if it is right. i would appreciate if somebody could give me a step by step guide for the same.

[D@n]

@Vishnuk,

The IP cores Xilinx provides are not intended to be "modified for use".  They're intended to be used as is.  The UART 16550 core is one such core.  It is not intended to be modified, but to be used as is.  Some cores offer parameterization, some can be configured, but "modified" is typically beyond the scope.

This leaves you with a couple of options:

1. If you want to build a serial port echo using the UART 16550 core, you need to connect an AXI master to it.  Most of the instructional material will discuss creating a MicroBlaze CPU and then creating a bus for it to get instructions and data from.  You could then connect the UART16550 to that bus and write a program to query the UART16550 in a loop and write the results to the transmit half of the core.  This would create a serial port "echo".  It's also a horrendously complex place to start from simply from the number of things that could go wrong when setting it up.  If you are a beginning FPGA designer wanting to learn how to write VHDL, this is not where I would recommend you start.
2. You could also build your own AXI master to communicate with the UART16550 core--something less than a MicroBlaze, perhaps even much less than a CPU.
3. Xilinx also offers some other UART cores as well.  Perhaps one has a simpler interface that would be easier to interact with from VHDL.  Perhaps not.  You might be able to find something better by searching through their offerings.
4. A serial port is actually a fairly simple core to build.  If you are a beginner wanting to learn VHDL, this would be where I would advise you begin.  The other options above aren't really that great for teaching someone logic design--they're better options for someone who already knows and understands logic design.  I would recommend you build your own serial port using the 8N1 serial protocol (8 data bits, no parity, 1 stop bit) since that's the most common serial port line coding.  The baud rate you choose is somewhat up to you.  115,200 is common, but I'm aware of at least one terminal emulator only goes up as high as 9.6k.

If you go for building your own, then it should be very easy to connect the receiver directly to the transmitter to build an echo device.  Indeed, you can see how I did it myself using Verilog here.  That file is a bit curious simply because it was first written to support a serial port that would operate on any protocol (5,6,7,or 8 data bits, mark, space, odd, even, or no parity, 1 or 2 stop bits, arbitrary baud rates, etc) and could switch protocols at run time.  The resulting core turned out to be too complex for some of the FPGAs I've since needed to work with, and so I had to come back and write "lite" versions of my transmitter and receiver that only supported 8N1 and a constant baud rate.  A macro within the file controls whether or not the full or lite versions of the underlying serial port implementations are used.  My point?  Starting with the 8N1 protocol really isn't such a bad thing to do.

The one other thing I'd point out is that in my own Verilog beginner's tutorial, one of the tutorial's exercises is that of building a serial port.  It's a good task to learn from and early on.  Indeed, it's a good task to learn from long before you start playing with anything "AXI" or "AXI" related. If you are struggling to get your serial port to work in hardware, you can use blinky to your advantage to find out why or where it's failing too.  Once you get your own serial port working, debugging gets easier since you can then send debugging data over the serial port--but you sort of have to get past this task first in order to get there.  Hence the reason why I like teaching how to build a serial port early on.

Dan

[D@n]

@Vishnuk,

Looks like you got roughly the same answer from Xilinx's forums as well.

Dan