Basys 3 microblaze will not crossprobe

[FlyingBlindOnARocketCycle]

I am trying to play along with lab 3 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug940-vivado-tutorial-embedded-design.pdf

I can build the project and run it in Vitis but it just doesn't crossprobe as the tutorial says I should observe. 

Ideas?

Thanks

fboarc

[FlyingBlindOnARocketCycle]

I Finally figure it out! 

In the microblaze settings in vivado you have to set "microblaze debug module interface = Extended" to enable cross-trigger with a microblaze design.  The debug target settings in the software IDE will not have a cross-trigger check box when using a microblaze as it would if using a real processor.

[Ana-Maria Balas]

Hello @FlyingBlindOnARocketCycle,

To see the debug signals, you must use ILA IP in your design and connect them to the desired signal line/lines you want to debug.

In step 10 you run the software application from Vitis in Debug mode and you can set breakpoint where the application should stop.

In step 11 you need to go back to Vivado, while the Vitis is also opened and prepared for run. In Vivado, in Hardware Manager you have to connect to the target.

In step 12 you start the Logic Analyzer and follow the indications. Then while Vivado is connected and ILA is armed, you go back in the Vitis software platform Debug window, click MicroBlaze #0 and then click the Resume button.

Then the signals you connected to ILA for debug should appear in the Logic Analyzer window in Vivado.

[FlyingBlindOnARocketCycle]

I see from outline of steps that you have read the pdf link I referenced in my question. Thank you for taking time to do that. Did you happen to attempt to follow these steps yourself with the Basys3 hardware? I am using Vivado 2019.2 and following along very closely with the steps listed in the mentioned tutorial and yet upon clicking resume in step 12, the ILA does not trigger.

Thanks

fboarc

[Ana-Maria Balas]

I have not used Vitis yet. But it doesn't matter because I think that the problem you have it is not because of the Basys 3 or Vitis as long as the application is running as expected.

You should familiarize with debugging with ILA first, and then you will understand much more easier how it works with Vitis or SDK. Also I would recommend you to use the ILA in native interface in the beginning.

I use the Logic Analyzer with Xilinx SDK concomitantly to debug the signals, and the steps are the same. Program the board with the bitstream, then load the .elf from SDK and then see what happens in Logic Analyzer in Vivado.

You should make an application that runs in a loop. Some application like reading constantly the state of multiple buttons. Start the application in Vitis and let it run, then go back to Vivado and click the Run Trigger button.

Also try to add a signal in the Trigger Setup window and put some condition on it. Example if you press the button X, then the trigger should start when the buttonX_signal == '1'.

 

 

[FlyingBlindOnARocketCycle]

The tutorial we are discussing does create a software design with a loop.  It has the user put a while(1) loop in the code so the peripheral test will continue.  I am somewhat familiar with using ILA's.  I can set a trigger in the ILA and it functions as expected.  I can also set a break point in the C code and what the code stop at the break point.  All is working with the 1 solo exception of cross probing which simply does not trigger the ILA. A break point in the C code does not trigger the ILA.  Also when manually setting a trigger value in the ILA, the running debug code does not stop as if has hit a break point even though the ILA does trigger.

 

[Ana-Maria Balas]

 A break point in the C code won't trigger the ILA. A trigger value set in the Logic Analyzer window will not stop de application to run in SDK even if it's running in debug mode.

The Logic Analyzer window behaves like an oscilloscope with the difference that it doesn't run continuously,  the acquisition of data begins by pressing the Run Trigger button or setting a trigger.

[FlyingBlindOnARocketCycle]

2 hours ago, Ana-Maria Balas said:

 A break point in the C code won't trigger the ILA. A trigger value set in the Logic Analyzer window will not stop de application to run in SDK even if it's running in debug mode.

The Logic Analyzer window behaves like an oscilloscope with the difference that it doesn't run continuously,  the acquisition of data begins by pressing the Run Trigger button or setting a trigger.

I don’t think you are reading the tutorial very closely. Page 96 clearly states a break point in the code triggers the ILA. The fact that this is not working is the whole point of my question.

3. In the Vitis software platform Debug window, click MicroBlaze #0 and then click the Resume button.
The code will execute until the breakpoint set on line 50 in testperiph.c file is reached. As the breakpoint is reached, this triggers the ILA, as shown in the following figure.

[Ana-Maria Balas]

My example was about working with SDK and I asumed it is the same with Vitis.

It's great that with Vitis you can do that. Did you enable cross-triggering as it says here https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1371115136.html ?

Later Edit: Cross-Triggering can be done also in SDK. I did not know this, until I researched about this topic. https://www.xilinx.com/html_docs/xilinx2018_1/SDK_Doc/SDK_tasks/task_enable_cross_triggering.html