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Hi,

I am designing a project like your ZYBO Video Workshop, Paris, FRANCE,23.03.2017 document. I did step by step, but I could not reach the sobel edge detection applied result.
I may have done something wrong during the edge_detect block creation phase. Because there was no problem before. I added the relevant block to the diagram using your outs, but again I could not reach the result on the screen.


I saw that others also encountered problems in the forms. Is there any update in tutorial?
Could you help me with this problem?

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Describe the issue you are having in more exact terms. I understand the bitstream builds successfully, but you can see no image in the monitor. Correct me, if I am wrong.

In the early stages of the workshop there is a passthrough pipeline without any processing. Does that work?

If it works without the edge_detect module, you either wired the block wrong or the edge_detect timing requirements are not met. Verify the optimization directives in HLS.

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Yes, you are right. I cannot see result on the screen in the last step of the project.

The transparent structure was working before the HLS block intervened. the image was transferred exactly. Everything was correct without edge detection.

If the project in the workshop was tried, compiled and ready, shouldn't we be successful using the same board and the same program as the previous step?

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Hi,

I have same problem.

I had followed the workshop step by step.

First step was succesful.  FPGA blocks took view from HDMI and gave same view to VGA succesfully but at the second step (after adding HLS block) i couldn't see anything. I guess the problem on the HLS edge dedection block.

I think i didn't make any mistake because i am following your workshop. If it is workshop,  the project should be validated and working (and isntructions should be clear as cristal ).

If i am using the workshop codes and directives; it shouldn't be revelant with timing requirements (I think.) (if there is time issue i think it should be added to ucf as constrain). We are using same board (zybo) and same codes.

On this forum i saw someother people have same issue, check the bilal's answer.

So i am stuck at that point as friend above.

 

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Hi @xyz, @den_ya,

It's an interesting issue you are having and unfortunately there might be a series of reason for which this is happening. Lets start by first knowing exactly what you have.

1. Do you have the resource materials as well as the Workbook or only the Workbook?

2. What version of Vivado are you using?

3. In your final version of the project (with the HLS IP) do you have the control interface active (ap_ctl)? If yes then make sure that the ap_start and the rst_n pins are connected to a const 1 signal.

Once I know these answers I can provide more help

-Ciprian

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