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Adept Asynchronous Parallel Interface Typo?

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Hello Digilent!

I am currently trying to build FPGA logic to match the DEPP standard.  However, when looking through the Adept SDK documentation, and in particular the "Digilent Asynchronous Parallel Interface (DEPP)" standard, I noticed that the timing diagrams on pages 3 and 4 for both data and address transactions depended on the address strobe line.  Is this a typo?  Shouldn't the data write and data read transactions be dependent upon the DSTB or data strobe line?

Thanks!

Dan

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Hi Dan,

Yes that is a typo. That signal should be called DSTB for both the Data write and Data read diagrams. Thank you for catching this. I'll do my best to get this corrected.

 

Thanks

Tommy

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Hi Dan,

I apologize for not getting back to you sooner. I have asked some of our engineers about this who are more experienced with Adept than I; they'll get back to you here on the forum.

Thanks,
JColvin

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