BANDI Posted March 18, 2020 Share Posted March 18, 2020 Hi., Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter. Upto bit stream is done and exported to SDK Successfully. After creating Application and adding files it is showing errors. Kindly help regarding this Version: Vivado 2018.2.1 Link to comment Share on other sites More sharing options...
iyer25 Posted January 26, 2021 Share Posted January 26, 2021 13 minutes ago, elodg said: For Linux and V4L2 integration, the Xilinx MIPI CSI-2 subsystem should be used. could you please tell me if my understanding is right or wrong here. https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases/tag/v2019.1-1?_ga=2.167092222.1978256034.1611579035-2037839658.1594589074 this is the design I am using and I need to create Linux application for four cameras. Can I use this hdf file for creation of petalinux project ? and During the petalinux project- I need to integrate V4L2 and use Xilinix mipi subsystem, connect the end to end node points for successful device tree generation. My main objective is to create linux (FPGA implementation)application using FMC PCAM cameras (2/4 cameras) with zedboard. My another question is if I can use this example desgin or need to create one to reach my goal. Link to comment Share on other sites More sharing options...
elodg Posted January 26, 2021 Share Posted January 26, 2021 https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO is a Vivado+SDK standalone design using Digilent MIPI IPs. For a Petalinux-based application you need to start from scratch. Link to comment Share on other sites More sharing options...
elodg Posted January 26, 2021 Share Posted January 26, 2021 You may use these (unpublished/WIP) projects as inspiration: https://github.com/Digilent/Zybo-Z7-OS/tree/20/Petalinux/next https://github.com/Digilent/Zybo-Z7-HW/tree/20/Petalinux/next https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/demos/petalinux Link to comment Share on other sites More sharing options...
iyer25 Posted January 27, 2021 Share Posted January 27, 2021 21 hours ago, elodg said: https://github.com/Digilent/Zybo-Z7-HW/tree/20/Petalinux/next Thank you for the links. I cant really see the design here. how can I extract the vivado file here to use as an example Link to comment Share on other sites More sharing options...
elodg Posted January 27, 2021 Share Posted January 27, 2021 From the repo readme: Quote For instructions on how to use this repository with git, and for additional documentation on the submodule and branch structures used, please visit Digilent FPGA Demo Git Repositories on the Digilent Wiki. https://reference.digilentinc.com/reference/programmable-logic/documents/git#vivado_hw_projects Link to comment Share on other sites More sharing options...
iyer25 Posted March 3, 2021 Share Posted March 3, 2021 hello, I was trying to create an application and running on the zedboard with boot images created by the petalinux for checking the drivers part. I was able to boot and check the errors two days ago. I have the boot image screenshot which stops in the middle now. any help for this problem ? Quote =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2021.03.03 18:20:20 =~=~=~=~=~=~=~=~=~=~=~= Unknown command 'æ`æx~þøæ`ææ`ææ`ææ~xð~~xð~' - try 'help' Zynq> Unknown command 'æ`æx~þøæ`ææ`ææ`ææ~xð~~xð~' - try 'help' Zynq> boot Device: mmc@e0100000 Manufacturer ID: 6 OEM: 524b Name: MSBus Speed: 50000000 Mode : SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.3 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes 4190944 bytes read in 248 ms (16.1 MiB/s) ## Loading kernel from FIT Image at 10000000 ... Using 'conf@system-top.dtb' configuration Verifying Hash Integrity ... OK Trying 'kernel@1' kernel subimage Description: Linux kernel Type: Kernel Image Compression: uncompressed Data Start: 0x10000108 Data Size: 4167248 Bytes = 4 MiB Architecture: ARM OS: Linux Load Address: 0x00008000 Entry Point: 0x00008000 Hash algo: sha1 Hash value: ce9029c231cdfe6466bd8a112188c4acfaa6e8de Verifying Hash Integrity ... sha1+ OK ## Loading fdt from FIT Image at 10000000 ... Using 'conf@system-top.dtb' configuration Verifying Hash Integrity ... OK Trying 'fdt@system-top.dtb' fdt subimage Description: Flattened Device Tree blob Type: Flat Device Tree Compression: uncompressed Data Start: 0x103f9858 Data Size: 21783 Bytes = 21.3 KiB Architecture: ARM Hash algo: sha1 Hash value: 2f96fd6acea5be5dd83132fdf271d64937519788 Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x103f9858 Loading Kernel Image ... OK Loading Device Tree to 07ff7000, end 07fff516 ... OK Starting kernel ... Booting Linux on physical CPU 0x0 Linux version 4.19.0-xilinx-v2019.1 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT Wed Mar 3 16:20:43 UTC 2021 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache OF: fdt: Machine model: Zynq Zed Development Board bootconsole [earlycon0] enabled Memory policy: Data cache writealloc cma: Reserved 16 MiB at 0x1f000000 random: get_random_bytes called from start_kernel+0x80/0x3c4 with crng_init=0 percpu: Embedded 16 pages/cpu @(ptrval) s35916 r8192 d21428 u65536 Built 1 zonelists, mobility grouping on. Total pages: 130048 Kernel command line: console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 492980K/524288K available (6144K kernel code, 206K rwdata, 1628K rodata, 1024K init, 246K bss, 14924K reserved, 16384K cma-reserved, 0K highmem) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xfff00000 (3072 kB) vmalloc : 0xe0800000 - 0xff800000 ( 496 MB) lowmem : 0xc0000000 - 0xe0000000 ( 512 MB) pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) modules : 0xbf000000 - 0xbfe00000 ( 14 MB) .text : 0x(ptrval) - 0x(ptrval) (7136 kB) .init : 0x(ptrval) - 0x(ptrval) (1024 kB) .data : 0x(ptrval) - 0x(ptrval) ( 207 kB) .bss : 0x(ptrval) - 0x(ptrval) ( 247 kB) rcu: Preemptible hierarchical RCU implementation. rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. Tasks RCU enabled. rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 efuse mapped to (ptrval) slcr mapped to (ptrval) L2C: platform modifies aux control register: 0x72360000 -> 0x72760000 L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000 L2C-310 erratum 769419 enabled L2C-310 enabling early BRESP for Cortex-A9 L2C-310 full line of zeros enabled for Cortex-A9 L2C-310 ID prefetch enabled, offset 1 lines L2C-310 dynamic clock gating enabled, standby mode enabled L2C-310 cache controller enabled, 8 ways, 512 kB L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001 zynq_clock_init: clkc starts at (ptrval) Zynq clock init sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns Switching to timer-based delay loop, resolution 3ns clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns timer #0 at (ptrval), irq=17 Console: colour dummy device 80x30 Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) CPU: Testing write buffer coherency: ok CPU0: Spectre v2: using BPIALL workaround CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x100000 - 0x100060 rcu: Hierarchical SRCU implementation. smp: Bringing up secondary CPUs ... CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 CPU1: Spectre v2: using BPIALL workaround smp: Brought up 1 node, 2 CPUs SMP: Total of 2 processors activated (1333.33 BogoMIPS). CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns futex hash table entries: 512 (order: 3, 32768 bytes) pinctrl core: initialized pinctrl subsystem NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations cpuidle: using governor menu hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. hw-breakpoint: maximum watchpoint size is 4 bytes. zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval) zynq-pinctrl 700.pinctrl: zynq pinctrl initialized e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 3125000) is a xuartps `¬ËתLed console [ttyPS0] enabled bootconsole [earlycon0] disabled bootconsole [earlycon0] disabled GPIO IRQ not connected XGpio: gpio@41200000: registered, base is 1020 GPIO IRQ not connected XGpio: gpio@41210000: registered, base is 1016 vgaarb: loaded SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb media: Linux media interface: v0.10 videodev: Linux video capture interface: v2.00 pps_core: LinuxPPS API ver. 1 registered pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> PTP clock support registered EDAC MC: Ver: 3.0.0 FPGA manager framework Advanced Linux Sound Architecture Driver Initialized. clocksource: Switched to clocksource arm_global_timer NET: Registered protocol family 2 tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes) TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 4096 (order: 3, 32768 bytes) TCP: Hash tables configured (established 4096 bind 4096) UDP hash table entries: 256 (order: 1, 8192 bytes) UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing. hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available workingset: timestamp_bits=30 max_order=17 bucket_order=0 jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) io scheduler mq-deadline registered io scheduler kyber registered dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330 dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 Link to comment Share on other sites More sharing options...
iyer25 Posted July 10, 2020 Share Posted July 10, 2020 here is the picture. Link to comment Share on other sites More sharing options...
vicentiu Posted March 18, 2020 Share Posted March 18, 2020 what errors is it showing? Link to comment Share on other sites More sharing options...
BANDI Posted March 18, 2020 Author Share Posted March 18, 2020 Hi Vicent, the folllwing are errors 1. Description Resource Path Location Type fatal error: uart.h: No such file or directory uart_ps.c /new/uart line 61 C/C++ Problem 2.Description Resource Path Location Type make: *** [uart/uart_ps.o] Error 1 new C/C++ Problem 3. Description Resource Path Location Type recipe for target 'uart/uart_ps.o' failed subdir.mk /new/Debug/uart line 18 C/C++ Problem Link to comment Share on other sites More sharing options...
BANDI Posted March 18, 2020 Author Share Posted March 18, 2020 #include <stdarg.h>#include "../../src/uart/uart.h" // here one error # Each subdirectory must supply rules for building sources it contributes uart/%.o: ../uart/%.c //here another error @echo 'Building file: $<' @echo 'Invoking: ARM v7 g++ compiler' arm-none-eabi-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../pcan_demo_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" @echo 'Finished building: $<' @echo ' ' Link to comment Share on other sites More sharing options...
BANDI Posted March 18, 2020 Author Share Posted March 18, 2020 16 minutes ago, vicentiu said: what errors is it showing? Link to comment Share on other sites More sharing options...
JColvin Posted March 19, 2020 Share Posted March 19, 2020 Hi @BANDI, When you created the new application project as per the setup guide listed in the readme for the demo (available here), did you select C++ as the target software language? Additionally, could you show us what appears when you click the "Modify this BSP's Settings" button that on the system.mss tab that you have on your screen? Otherwise, one thing that I tend to do is to right-click on the BSP folder and have it Regenerate BSP sources to see if that helps SDK resolve some of those errors. I ran through the Zedboard FMC Adapter demo in Vivado 2018.2 but did not encounter those errors. Thanks, JColvin Link to comment Share on other sites More sharing options...
BANDI Posted March 20, 2020 Author Share Posted March 20, 2020 6 hours ago, JColvin said: Hi @BANDI, When you created the new application project as per the setup guide listed in the readme for the demo (available here), did you select C++ as the target software language? Additionally, could you show us what appears when you click the "Modify this BSP's Settings" button that on the system.mss tab that you have on your screen? Otherwise, one thing that I tend to do is to right-click on the BSP folder and have it Regenerate BSP sources to see if that helps SDK resolve some of those errors. I ran through the Zedboard FMC Adapter demo in Vivado 2018.2 but did not encounter those errors. Thanks, JColvin Link to comment Share on other sites More sharing options...
BANDI Posted March 20, 2020 Author Share Posted March 20, 2020 Ho Colvin, I attached the screenshots please check. I'm done with regenerate BSP also but still facing same issue Note: I'm soing this in Ubuntu 16.04 Linux Link to comment Share on other sites More sharing options...
JColvin Posted March 20, 2020 Share Posted March 20, 2020 Hi @BANDI, Using Ubuntu should not be an issue in this situation as far as I am aware. I do apologize that I wasn't clear in what I was hoping to see on the Modify this BSP's settings page. What I'm looking for is the drivers that were are being used for the MIPI_D_PHY_RX and the video_scaler. I have attached a showing how you can find this screen; you just need to click on the "drivers" dropdown after clicking on the "Modify this BSPs settings" button. Your pop-up is still on the "Overview" dropdown. The reason I am asking for this is because the drivers for the MIPI_D_PHY_RX and the video_scaler do not always correctly import the Digilent made driver and just use the "generic" one. If this is the case, you will need to add them in as described in step 16 of the readme. Please let me know if you have any questions about this. Thanks, JColvin Link to comment Share on other sites More sharing options...
iyer25 Posted July 1, 2020 Share Posted July 1, 2020 Hi., Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter.(dual pcam code ) also could you provide the right github link for four cameras connection. Upto bit stream is done and exported to SDK Successfully. After creating Application and adding the files, I have followed evrything as per given on the github. I have tasks to do -- TODO cams sharing same power enable, TODO CSI-2, D-PHY config here. could you please tell me what changes I need to make and I have zero errors with 1 warning and 2 tasks Kindly help regarding this Version: Vivado 2018.2.1, windows Thanks in advance Link to comment Share on other sites More sharing options...
JColvin Posted July 1, 2020 Share Posted July 1, 2020 Hi @meghuiyer@gmail.com, The 4 camera connection is the same GitHub link that is provided in this specific post here: https://forum.digilentinc.com/topic/19768-pcam-5c-with-zedboard/?do=findComment&comment=54467. The dual camera GitHub link is available here: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-Dual-Camera. The warning and 2 infos/tasks I presume you have (the warning and 2 infos I have on my 4 camera FMC project are: warning: this statement may fall through [-Wimplicit-fallthrough=] ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 246 C/C++ Problem Info 1: #pragma message: For the sleep routines, Global timer is being used xtime_l.h /ZedBoard_FMC_Pcam_Adapter_DEMO_bsp/ps7_cortexa9_0/include line 89 C/C++ Problem Info 2: here ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 247 C/C++ Problem) can likely be ignored as they are informing you of details that are directly built into the Xilinx material; i.e. the first info message is simply repeating line 89 in xtime_l.h verbatim. I am a little confused on your tasks. Each of the ports on the FMC Pcam adapter already use the same power enable, PWUP. Additionally, the purpose of the demo is to facilitate the MIPI and CSI-2 communication. The D-PHY was already taken care in the layout of the board. Thanks, JColvin Link to comment Share on other sites More sharing options...
iyer25 Posted July 1, 2020 Share Posted July 1, 2020 Hi, thanks for the reply. I tried ignoring these and nothing is displayed or has any message. I cant activate the camera also nor displays any message on the screen. Could you please help me with this?? Could you please give me link for four cameras. I have checked with the link here, I cant find hls code (https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO?_ga=2.80883543.1969551905.1593633979-207701440.1588249171) --Download the most recent release ZIP archive ("FMC-Pcam-Adapter-2018.2-*.zip") from the "repo's releases" page.-- I cant find the code. also this says out of date synthesis. Is that okay to run the code ?? Link to comment Share on other sites More sharing options...
JColvin Posted July 3, 2020 Share Posted July 3, 2020 Hi @meghuiyer@gmail.com, Here is the correct link to the release page: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases. The link in step 1 of the readme is being corrected as I'm typing. You will need to generate the bitstream (and the synthesis will be out of date) as per step 4 before exporting the project to SDK. After the bitstream is generated (for the 2018.2 project, I don't think you need to generate a bitstream for the 2019.1 release), did you then import the sources into the SDK project? Thanks, JColvin Link to comment Share on other sites More sharing options...
iyer25 Posted July 3, 2020 Share Posted July 3, 2020 Hi thank you for the new link. It works but I couldn't turn on Part A, Port B cameras. Is it because of cycle mating ? Have a good day meghana Link to comment Share on other sites More sharing options...
JColvin Posted July 8, 2020 Share Posted July 8, 2020 Hi @meghuiyer@gmail.com, I am not sure what the issue might be. I have reached out to another engineer for their input on this. Thanks, JColvin Link to comment Share on other sites More sharing options...
JColvin Posted July 9, 2020 Share Posted July 9, 2020 As a friendly follow-up, can you attach a picture of your setup so I can double check that the flatwire cables are attached correctly? Thanks, JColvin Link to comment Share on other sites More sharing options...
elodg Posted August 4, 2020 Share Posted August 4, 2020 Did you forget to install the cable drivers perhaps? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf#G5.401934 Link to comment Share on other sites More sharing options...
JColvin Posted July 10, 2020 Share Posted July 10, 2020 Hi @meghuiyer@gmail.com, The cables look good. Does the camera which looks like it's attached to Port C work? Do you get an errors in the serial terminal with regards to the cameras attached to ports A and B? I presume you are not getting anything on the screen output based on the phrase "I couldn't turn on Port A, Port B cameras" Thanks, JColvin Link to comment Share on other sites More sharing options...
iyer25 Posted July 12, 2020 Share Posted July 12, 2020 Hi Port C works well and It doesn't display anything for port A and Port B Thanks Meghana Link to comment Share on other sites More sharing options...
Question
BANDI
Hi.,
Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter.
Upto bit stream is done and exported to SDK Successfully.
After creating Application and adding files it is showing errors.
Kindly help regarding this
Version: Vivado 2018.2.1
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