Board Files are out of date?

[Clyde]

Are there any plans to update the board files for the Zybo Z-10?  Lots of things are missing from it such as the DDR3 component and the pulldowns for the PMODS, such as for the WiFi.  The Arty board files seem to be complete, including DDR3.

 

I am trying to get the Internet of things example running and the video is great, but it is not all there. A pdf of the finished block design would be a tremendous help..  

 

I have scoured the internet and nothing comes up to help.  Likewise, many examples are posted which claim to be a compiled and working example of some of the demos, but they are all broken in some fashion or another.

 

I have spent $250 on hardware that I can't get to go.  Either I am totally missing something so fundamental, or the board files are faulty.

 

I have been able to Microblaze designs to work on the Arty, but I am stuck with the Zybo.

[JColvin]

Hi @Clyde,

Because the Zybo Z7-10 has an ARM core, the preset file for the Zynq IP handles the DDR3 for you as it is directly connected to the PS. The way to get this set up is described in our guide here: https://reference.digilentinc.com/vivado/getting-started-with-ipi/start, specifically on step 4.5 you can see the DDR implemented for you on the Zynq7 Processing System IP.

There is some more information describing how to get this going on this post here: https://forum.digilentinc.com/topic/17224-pmod-wifi-sdk-problem/?do=findComment&comment=52875, that I did with the Zedboard; the block design (presuming you are working with the Pmod WiFi) will look the same as it does for the Zybo Z7-10 as the specific preset configurations for the Zynq IP block are visually abstracted away.

What version of Vivado are you using?

Thanks,
JColvin

[Clyde]

Thanks.  This was a big help as I was able to build the hardware platform, although it came with warnings about an IP repository I found "somewhere" on the internet with definitions for the PMOD devices, including the WiFi module.  I still have no clue if I correctly set up any of the clocks. I set the PS clock to 33.3333 MHz (which was a difference) because that is what is used on the Z7-10.

However, there is an  lot of handwaving when it comes to the application software.  Where to find that?  Where is the proper IP repository for the PMOD devices?

To answer your earlier question, I have tried 2017.4, 2018.2 and 2019.2.  I have given up on 2019.2 as I have not been able to figure out Vitis at all.  At least with the other two, SDK is still there.

I tried all three believing it was a version issue, which it is not.

 

Clyde

[JColvin]

Hi @Clyde,

We have our official IP repository available on our GitHub here: https://github.com/Digilent/vivado-library.

In terms of getting Pmods up and running properly, I follow the Pmod IP guide that we have here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start. There is a table at the top of the guide that lets you know if there are changes you need to make from the defaults that are set; in the case of the WiFi, an interrupt will be needed as well as DDR, though again the DDR is automatically configured for you through our board presets on the block design. And for what it's worth, I was able to get the Pmod WiFi working with a Zynq board on the last post of the forum thread I linked previously and attached my project files for 2019.2 (the original link was confirming the 2019.1 design), so hopefully that would be a good resource for you in terms of working with Vitis.

I can run through the project in a different version if you need it.

Thanks,
JColvin

[Clyde]

I am still lost.  I have installed the latest repository and built a block design with the zynq 

uart, and a gpio.  It won't implement.

Place Design[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following are banks with available pins: 
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   RangeId: 1  has only 0 sites available on device, but needs 1 sites.
    Term: uart_rtl_rxd

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |     3 | LVCMOS33(3)                                                            |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |     5 | LVCMOS33(5)                                                            |                                          |        |  +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   100 |     8 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | sws_4bits_tri_i[1]   | LVCMOS33        | IOB_X0Y2             | P15                  |                      |
|        | sws_4bits_tri_i[2]   | LVCMOS33        | IOB_X0Y41            | W13                  |                      |
|        | sws_4bits_tri_i[3]   | LVCMOS33        | IOB_X0Y32            | T16                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | leds_4bits_tri_o[0]  | LVCMOS33        | IOB_X0Y54            | M14                  |                      |
|        | leds_4bits_tri_o[1]  | LVCMOS33        | IOB_X0Y53            | M15                  |                      |
|        | leds_4bits_tri_o[2]  | LVCMOS33        | IOB_X0Y99            | G14                  |                      |
|        | leds_4bits_tri_o[3]  | LVCMOS33        | IOB_X0Y93            | D18                  |                      |
|        | sws_4bits_tri_i[0]   | LVCMOS33        | IOB_X0Y61            | G15                  | *                    |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

I implemented a microblaze with the same boards files, and that implemented, but failed, of course on the bitstream generation.

What could I be doing wrong?

[JColvin]

Hi @Clyde,

Could you attach your block design? Additionally, did you change the .xdc file at all? A microblaze design on Zynq is difficult to use nicely, plus not necessarily needed since there is an ARM processor on the board so there is usually no specific need to create a different microprocessor.  I would also like to confirm that you selected the Zybo Z7-10 was selected as the board part as shown in Section 1.5 of the Getting Started with the Vivado IPI guide: https://reference.digilentinc.com/vivado/getting-started-with-ipi/v2019.2#section15.

Thanks,
JColvin

[Clyde]

What I did was download the newest board files and put them in place and built an existing, working microblaze design on my Arty-35.  This all worked and I was able to generate a bitstream.

Then I created a new design for the Zybo z-10, essentially the same design and if I recall correctly, I got through the implementation phase, but bitstream failed, as it should.  The LEDs are all in the wrong place and the clock too, etch.  This failure all made sense.

Then I created a new block design, simple, and the implementation fails.  Attached is the block design.

Linux1.pdf

[Clyde]

I should add the block design was created without any manual wiring, just block automation and connection assistance at the appropriate times.

 

Clyde

[JColvin]

Hi @Clyde,

You do not need to add the UART material to the Zynq block design; the UART is connected directly to the processing system (PS, that is, the ARM core) so the Zynq block will handle the UART side of things for you. Adding the UART manually is required for MicroBlaze reliant boards though as they do not have a microprocessor already built in for them.

I have attached what a block design for the Zybo Z7 including the Pmod WiFi, LEDs, and buttons should look like.

Thanks,
JColvin

ZyboZ710-PmodWiFi-blockDesign.pdf

[Clyde]

Ok, this is helpful, but in your diagram there is no external serial port visible to me.   I see in the Zynq setup the Uart is enabled, but how to get it out?  What I am really trying to do, to get started is to build a simple linux platform with a serial port, buttons and LEDs and the wifi so I may try my hand at embedded linux.  This is a really simple hardware platform and I feel like I am the first person in the world to do this (can't be true).   

I am attaching a screen shot of the Project management screen and the boards tab.  When I right click on any of the PMODs, I do not get any choices to connect up the Wifi module.

Lastly, In a previous attempt where I was "magically" able to get the wife module on PMOD JC, I did hook up the concat block and enable the interrupt as you did, but apart from changing the width of the ports on the concat, I have no clue as to the logic function it is to perform.  I stumbled across a Vivado library with PMODs, which I added as IP, but I don't remember where I found it, nor do if I know it is correct.

In all of this I realize this is a very powerful system and I am so close, yet so far.  Thanks for your help thus far.

 

Clyde

config.pdf

[Clyde]

Ok, now I see that by checking the uart boxes in the I/O configuration, the serial port is there.... it just does not show up in the diagram.

 

I think with help with the concat logic and the PMOD repository question I am good to go.

 

What I have learned is Zynq is not so external component intensive as a Microblaze design is.

Clyde

[JColvin]

Hi @Clyde,

That is correct; much of the material is wrapped up inside of the IP block. If you double click on the Zynq processing block you can see a lot of the material, such as the UART, present inside of it. With regards to connecting to the board via a serial terminal later, all you need to do is have the design/application loaded onto the board and have the board connected to your computer via a USB cable, and then connect to it's COM port with a serial terminal such as TeraTerm.

I do get that having a lot of the material abstracted away is a bit disorienting (and frustrating if you want to control minute details) when you are used to having to do everything yourself, but it can lend itself to some easier development when a number of peripherals are handled for you. There are pros and cons associated with this (trading convenience with processor overhead), but that's the case with most things.

Let me know if you have any further questions.

Thanks,
JColvin

[Clyde]

I think I am largely on my way.  I just built a quick little hello world hardware platform, created a bitstream and it's in the FPGA.  Now its up to me to remember how to get the SDK to play, but it will come.  Thanks again.

Clyde