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Hello,

I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core.

Can you helo me about these issues as soon as possible?

 Thank you.

Best Regards.

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Posted (edited)

this is for Zynq, right? Are you aware of the DDR configuration settings inside the PS block?

Not sure if it makes sense to design your own "IPCORE" - isn't the DDRC subsystem a hard macro (not running on programmable logic but hardwired gates)?

Edited by xc6lx45

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Posted (edited)
5 minutes ago, xc6lx45 said:

this is for Zynq, right? Are you aware of the DDR configuration settings inside the PS block?

Not sure if it makes sense to design your own "IPCORE" - isn't the DDRC subsystem a hard macro (not running on programmable logic but hardwired gates)?

Hi,

 I am working Ultrscale MpSOC+  and I added DDR4 which is provided from vivado but  I did not recustoimize that's why I want to create my DDR4 IpCORE.Also I want to access DDR in PL part.

Edited by ozden.erdinc

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Hi @xc6lx45,

I am working  Zynq Ultrscale MpSoC+, I didn' t configure the PS DDR settings. Is DDR that you say belong to PS  side , am I wrong?. I dont want to use PS side DDR. I want to use only PL side DDR. My mind is confuse. But I want to write and read data patetrint into the PL side DDR?

Can you help me this issue?

Thank you.

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I can only speak about myself but usually I'm reluctant to give answers that are much longer than the question.

If you describe more what you intend to do (e.g. just hook up DDR4 in a standard configuration, or maybe design a custom DRAM controller on PL for some exotic application e.g. component testing or hacking / security), you might get more meaningful answers.

I suspect that your whole idea of "custom DDR4 core" is essentially a dead end, not strictly impossible but very difficult and limited in performance. Depending where the idea came from, this might be a "research" topic (where higher risks are acceptable compared to "development"). If anybody knows otherwise, please chime in...

 

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It depends how the board was designed if the DDR was wired to the PS or PL, though if you are using an SoC, then it may be more pertinent to have it go to the PS so that the processor has the access it needs to run properly. I don't know if there is necessarily a strict requirement that an SoC is directly connected to DDR, though all of the Digilent boards do this. Digilent has our own presets that we use to work with DDR, those are available with in the board files on our GitHub: https://github.com/Digilent/vivado-boards/tree/master/new/board_files. Otherwise Xilinx has a number of materials for DDR and their LogicCORE IP which to my understanding is provided free of charge (provided you comply with the Xilinx End User License Agreement).

Thanks,
JColvin

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Thank you @JColvin. By the way How can I store my data in seven mig series ddr3 ip core. Can you suggest any idea?

 Or can I write custom fifo ip core with axi4 interface, after that I will connect with ddr3 ip core? Is that possible  or not?

 

Thank you.

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@ozden.erdinc,

You can always write an AXI master to interact with the Zynq's ports.  Such a master would then be able to interact with the DDR4 memory controlled by the Zynq.  This article discusses the logic required for a simpler version of such a master.  You'd still need to create a custom IP in order to place this logic into something functional.  (Beware, lots of Xilinx's custom IP cores have bugs in them--still hoping for a fix in 2020.1.)

Dan

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