creating a latch data

[Vishnuk]

Hi,

i am receiving a data and then storing it in variable, i need it to hold that value untill new data arrives, the variable happens to hold data for few clock cycles and then vanish. Can somebody help me with it i tried below statements

buf <= dfin when (valid = '1') else buf;

 

process(clk)
   begin
   if (rising_edge(CLK)) then
   if valid ='1' then
    buf <= dfin;
   end if;
   end if;
   end process;

[D@n]

@Vishnuk,

The first of those will likely synthesize into a latch--something FPGAs can't handle very well.  The second looks like a decent solution.  What happened when you tried it?

Dan

[Vishnuk]

the dfin value gets refreshed soon.for both the cases the value gets stored in buf for short instance and then vanishes