Creating a Custom IP core using the IP Integrator

[sagar0077]

Creating a Custom IP core using the IP Integrator share exact process

[JColvin]

Hi @sagar0077,

Here is a link to Xilinx's guide directly on this process: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1118-vivado-creating-packaging-custom-ip.pdf. The link I provided is for 2019.1, but you can view the guide for other versions of Vivado by changing the "2019_1" in the url to whichever version you have available.

Thanks,
JColvin

[D@n]

@sagar0077,

Just be aware when you use this process, that the auto-generated code from the IP integrator has been broken for about 4 yrs or so.  You can read about the bugs in the AXI-Lite slave here, or the bugs in the AXI slave here.  Indeed, these bugs just impacted someone else this morning who was trying to figure out why the CPU and debugger just suddenly froze with his design.  You can find a better (working) AXI-Lite slave design here, and a better AXI slave design here.  While I haven't posted it yet, even the IP integrators AXI stream master is broken as well.

Dan

[chainastole]

There is a great tutorial from a collective of authors of University of Strathclyde on FPGA, which among all other interesting staff has a part on custom IP creation with accompanying lab. See http://www.zynqbook.com/download-book.php and http://www.zynqbook.com/download-tuts.html.

[D@n]

@chainastole,

I imagine there are a lot of AXI cores in the code for that tutorial.  I just picked one at random--the LED controller from the example code.

It's broken.  It doesn't even have the fixes within it for the write channel that Xilinx (eventually) made.

How is it broken and no one has noticed?  That was the topic of this blog post.  Turns out, it passes a first simulation test, but under certain cases and conditions that aren't often simulated it will hang the entire design.

Just FYI.

In other news, I simplified my example AXI-Lite core.  It fixes the bugs in Xilinx's demo cores.

Dan