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IBERT using Genesys-2 board PLL locking problem.


Question

I need to use the IBERT IP core on a Genesys-2 FPGA board. I am using FMC-SMA board to convert FMC into SMA. In the clock settings I am using the external clock source from pin AD-11/12 of 200MHz. 

But the problem is I am unable to get any output as PLLs are not locked.

I had followed the same steps with FMC board and all things where working fine. 

1. Can I use the internal clock in the clock setting. (I tried but getting the INFO:-  [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. )

2. Do I need a clock source on FMC-SMA board, as the place holder is provided but the oscillator is not provided by default.

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10 hours ago, zygot said:

You need to use an external clock source to the MGT quad where the transceivers that you want to test are. For the FMC transceivers this means one of the FMC_MGT_M2C pin pairs.

As I mentioned I am using external clock source available on Genesys-2 board using the pins AD-11/12. 

Using the same source I was able to get output on FMC board, but now I am using FMC-SMA board and I am unable to get any output (PLLs are not locked).

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13 hours ago, MohitSingh said:

As I mentioned I am using external clock source available on Genesys-2 board using the pins AD-11/12

Is that what I suggested? A prerequisite for doing your project is for you to read the Xilinx documentation on Seried7 transceivers and clocking and study the Genesys2 schematic.How do you know that this worked without a mezzanine board on the FMC connector ?:

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