Arty S7-25 DDR3 IP example init_calib_complete not getting asserted

[vack]

Hello friends,

I recently purchased Arty S7-25 to try one of our designs which needs DDR3 memory.(no MicroBlaze is used)

I was able to generate the IP(as per the mig.xml provided for Arty S7-25) and I am trying the relevant IP example.

Once I upload the design to the board I am seeing init_calib_complete is not getting asserted. (so is ui_clk_sync_rst and ddr3_reset_n).

Can anyone guide me to get this issue resolved. I can provide information and any required file.

Thanks a lot for your time!

[Ana-Maria Balas]

Hello @vack,

This is a tutorial for DDR3 interfacing without microblaze, but for a non-Digilent board. Maybe this can help you https://numato.com/kb/simple-ddr3-interfacing-on-skoll-using-xilinx-mig-7/

Also I think you can add the mig.prj file https://github.com/Digilent/vivado-boards/tree/master/new/board_files/arty-s7-25/E.0

[zygot]

@Ana-Maria Balas, offers a good suggestion. Opal Kelly has DDR example code projects using the Mig IP as well though you might have to be a registered user to download the FrontPanel framework to get it.

The toplevel Mig module isn't sufficient to use the Mig output products. You have to create your own controller to connect the Mig code to your own design. This generally involves a state machine to handle read and write requests. You can open the Mig generated example project and study that one project structure and code for guidance. If you are using VHDL I'm afraid that you are out of luck simulating your design; Verilog is required. That doesn't mean that you can't instantiate Verilog code into a VHDL design. I do this frequently. Even in an all Verilog design simulation isn't straight forward or easy. At least there are provisions for avoiding the long calibration period that makes simulation unbearable.

It would be a nice gesture for Digilent to help out its customers by getting one of its engineers to create a nice stand alone Verilog DDR Mig demo for one of its boards. Just a hopeful suggestion. It would be a nice off hours project... hint, hint...

[zygot]

@vack,

So how did you make out so far?

The Mig Ip can be troublesome. I just wasted a few hours trying to see if the Numato DDR tutorials work. I managed to get one for the MimasA7 working but only after lots of work-arounds and fixes. I've done more than a few standalone FPGA DDR designs and will got smacked by odd IP behaviors.

Again, it's astonishing that the only Digilent employee who responded to your question would point you to a competitor's web site for information that they never bothered to try fro themselves.