Zorroslade000 Posted February 21, 2020 Share Posted February 21, 2020 Hi, I followed the example for the spi srec loader. My vhdl/hardware design has many peripherals. The https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start example implies the same hardware design. Could a smaller hardware design (footprint) be implemented for the bootloader? Or is the same hardware design is used for all microblaze apps? Rob Link to comment Share on other sites More sharing options...
Ana-Maria Balas Posted February 24, 2020 Share Posted February 24, 2020 Hello @Zorroslade000, On 2/21/2020 at 9:23 PM, Zorroslade000 said: Or is the same hardware design is used for all microblaze apps? That tutorial prints Hello Word on Uart and uses DDR to store the application, so we can say for sure that the hardware design must contain an AXI UART Lite IP and a Memory Interface Generator (MIG) IP, so in this case, the application doesn't need all the peripherals from the hardware design. In this case the hardware design is smaller. But if your application require to use the peripherals, Uart, DDR (if the app you create is too big to fit into the BRAM), you'll have to add them all into the hardware design. So the size of the hardware design depends of the needs of your application. Of course you can make as many apps as you want with the same hardware and you'll have a different .elf file for each one of them. On 2/21/2020 at 9:23 PM, Zorroslade000 said: Could a smaller hardware design (footprint) be implemented for the bootloader? Each time you generate Bitstream, you generate a new hardware design file (.hdf). When you create an application, the SDK will load the board support package (BSP) from the hardware design file. BSP is a collection of libraries and drivers that is dependent on the hardware. As you saw when creating the SREC SPI Bootloader Application, it creates also a BSP. The compiler builds the SREC SPI Bootloader Application and creates an .elf file. When you program the board in 3.Generate Bitstream with BRAM initialized with bootloader step from tutorial, it creates a download.bit file, which is bitstream with the Executable and Linkable Format (ELF) file populated within the bitstream. Each time you change the hardware design, the BSP also changes, which means that the bootloader also changes. Link to comment Share on other sites More sharing options...
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Zorroslade000
Hi,
I followed the example for the spi srec loader.
My vhdl/hardware design has many peripherals. The https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start example implies the same hardware design. Could a smaller hardware design (footprint) be implemented for the bootloader? Or is the same hardware design is used for all microblaze apps?
Rob
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