Problem with Zybo Z7-20 Video Platform using Vivado HLS

[john_joe]

Dear all,

I am working with a video processing platform based on this project: https://www.hackster.io/adam-taylor/creating-a-zynq-or-fpga-based-image-processing-platform-e79394

I am using a Zybo Z7-20 and I am successful to make a simple passthrough buffer using VDMA. The project is described in the link above. However, when I create a project for a simple RGB2GRAY in Vivado HLS to insert block into the previous platform, I can't make it work (link for second project here: https://www.hackster.io/adam-taylor/using-hls-on-an-fpga-based-image-processing-platform-8f029f).

 

Using linux I can't co-simulate C/RTL in Vivado HLS, but if I use windows this is not an issue. I don't really know why, but it is topic for another question.

I generate the Vivado HLS block with ap_start hardwired to 1. Sometimes when I compile Vivado SDK I got some distortions with pixel flickering, but sometimes I can't even see any signals on the screen.

I am really lost as I don't understand what is happening. Without the HLS block I have no problems, but after inserting it is completely messed up.

I am enclosing the Vivado IP integrator block in PDF, as well the application code (hello.cpp) in the Xilinx SDK.

 

What I also tried instead of hardwiring the HLS block (using #pragma HLS INTERFACE ap_ctrl_none port=return) was to assign ap_start to 1 using a constant or connecting to a GPIO and driving it to 1 in the Xilinx SDK. None methods worked.

 

I am also attaching the whole project on this link: https://drive.google.com/file/d/1yM3upD4PuwHEXGZ_6M8O1-vZxLX5bIQP/view?usp=sharing. I am using Vivado 2018.3.

Please, I really need help and I do appreciate any feedback on this issue.

Thank you very much indeed.

design_1.pdf

 

hello.cpp

[BogdanVanca]

Hello @john_joe,

I will take a shot in the dark, and I will ask you what it is your target clock used for synthesis in HLS? It has to have the same period with the pixel clock from your Vivado design.