Zynq 7000 Baremetal with webpack.

[SigProcbro]

Hello,

I took everyone's advice and I played around with quartus and vivado and honestly I like quartus but I digress.

I think I want to get a hybrid SoC/FPGA device to play with instead of plain FPGA.

My question is, does the vivado webpack allow for full ARM baremetal development/debugging on the Zynq devices provided by digilent?

I found out rather late that Quartus "community" edition doesn't support baremetal development(a ridiculous omission since you're developing an FPGA hybrid but anywho....)

[xc6lx45]

I don't think there's anything to stop you.

As a starting point, you could create a "FSBL" (first-stage boot loader) project and cut it to size by deleting out anything you don't need. There are some essential parts you do need, such as powering up the level shifters between PS/PL, enable PL clocks etc.

IMHO, the easiest way to get there is to start from working code, even if you intend to not use a line of Xilinx code in the long run.

Note that when you do this, storing a faulty FSBL in flash memory can soft-brick your board when it prevents JTAG access on power-up. This is easy to fix if you're aware of the issue, takes some paper clip acrobatics to short a flash pin at power-up so it doesn't load from flash. Happens rarely, I think I had to do this once or twice in total. Some boards have boot mode jumpers, in this case no paper clip is required...

[SigProcbro]

1 minute ago, xc6lx45 said:

I don't think there's anything to stop you.

As a starting point, you could create a "FSBL" project and cut it to size by deleting out anything you don't need. There are some essential parts you do need, such as powering up the level shifters between PS/PL, enable PL clocks etc.

IMHO, the easiest way to get there is to start from working code, even if you intend to not use a line of Xilinx code in the long run.

Note that when you do this, storing a faulty FSBL in flash memory can soft-brick your board when it prevents JTAG access on power-up. This is easy to fix if you're aware of the issue, takes some paper clip acrobatics to short a flash pin at power-up so it doesn't load from flash. Happens rarely, I think I had to do this once or twice in total. Some boards have boot mode jumpers, in this case no paper clip is required...

Thanks. I don't have a problem with Xlinix code but I want to have full control of the ARM handed off to my program vs running under an OS.

My understanding for otherboards is a bootloader is run first prior to program entry.

Do you know if Xlinix SDK offers full debug support in baremetal?

[xc6lx45]

you can single-step through the FSBL, so that's probably a "yes".

Note that documentation may become an issue (regardless of webpack or paying license): The ARM core is Xilinx-customized, so the ARM documentation helps only to a point. For example, non-standard use of the cache controller is such a topic.

If you do want to use Xilinx libraries (but no OS) then forget everything I've written. It's a straightforward design flow => click through the menus to generate a new e.g. "Hello World" SDK project in standalone mode. Use an unmodified FSBL that loads your application. It's the obvious way ahead if you want to use external DRAM in your project, which is probably the case.

[SigProcbro]

On 2/11/2020 at 10:22 PM, xc6lx45 said:

you can single-step through the FSBL, so that's probably a "yes".

Note that documentation may become an issue (regardless of webpack or paying license): The ARM core is Xilinx-customized, so the ARM documentation helps only to a point. For example, non-standard use of the cache controller is such a topic.

If you do want to use Xilinx libraries (but no OS) then forget everything I've written. It's a straightforward design flow => click through the menus to generate a new e.g. "Hello World" SDK project in standalone mode. Use an unmodified FSBL that loads your application. It's the obvious way ahead if you want to use external DRAM in your project, which is probably the case.

Thanks,

Yeah I don't want to have to load the registers needed for ram timing or other init.

Does xilinix provide libs for baremetal programs? Where do I find the documentation? 

 

 

[xc6lx45]

For example here:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/oslib_rm.pdf

Links start on page 17.

The SDK creates the documentation for libraries you use in your project automatically.

This may be the easiest place to start: Create a minimal ZYNQ project or find one on the web, open in SDK. It should be somewhere in the file tree. You don't need hardware for that, just the Vivado Webpack download.