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chunho ok

Error importing Genesys2 OOB project sdk

Question

Hi,

I recently purchased a Genesys2 board and tried to recreate my OOB project. (Vivado2015.4)

There was no problem with the bit file generation.

However, when I import the SDK, I get the following error:

Is there a workaround?

Thank you,

Chunho Ok

 

111.JPG

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Hello @chunho ok,

I see that you have errors related to the board support package (bsp) sources. This happens if you don't have the updated sources or if you are not using the right HDF (Hardware Definiton File).

In Vivado, after the bitstream is successfully generated you need to export the hardware( File -> Export-> Export Hardware-> check Include bitstream box-> choose a location)

The easy way:

-right click on system_wrapper_hw_platform_0 and select Change Hardware Platform Specification -> select the HDF that you regenerated and exported.

-right click on the g2demo.bsp and select Re-generate BSP sources. Now the errors regarding the bsp sources should disappear.

Sometimes the SDK has some bugs and doesn't update properly the bsp sources and the errors remain, so I use the hard way.

The hard way:

1. Launch SDK in Vivado  (File-> Launch SDK -> use the same location as the one when you exported the bitstream)

2. The SDK will open and you will see system_wrapper_hw_platform_0 folder. Then you need to make a new application project ( you can set the name as g2demo).

After you created the application, it will appear g2demo and g2demo.bsp.

3. Copy the content of the g2demo from github SDK folder into the folder where you created the new application project.

Also copy the image dump folder to the same location.

Go into the SDK and refresh the folders (maybe you'll have to import the image dump folder to Project Explorer).

At the end you shouldn't have errors for the bsp.sources.

Let me know if it works.

 

Edited by Ana-Maria Balas

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Hi,

Thank you for your help.

SDK Error problem was solved after executing the above method.

However, if you download a newly created file, Displayport does not work. HDMI, OLED operation are all normal.

Is there a solution ??

Thank you,

Chunho Ok

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FPGA bit file and Micro Blaze file regenerate from the source file.

In case of the linked file, the following error occurs.

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
system_rgb2dpvid_1_0
system_rgb2dvi_0_0
system_rgb2vga_0_0

 

 

 

 

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We must clarify a few things:

1. Which Vivado version are you using? Which project version are you using?

2.  If you want to run the version Genesys2OOB_2016.4 you must use Vivado 2016.4. 

To solve the locked IP error you must add the Digilent Library Repository path explained in this tutorial at chapter 2. Add the Digilent Library Repository.

After you added the repository path, click Rerun

image.png.f6b266e1f0b167a6f2f319f14a6d9916.png

Then open Sources tab, right-click on system.bd -> Create HDL Wrapper -> Let Vivado manage wrapper and auto-update

image.png.4b16d9d9ee343d0b4187546fa5a74d5e.png

Then Generate Bitstream.

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I am using Vivado HL Design Edition 2016.4.

2016.4 version library registered but rgb2dvi ip has a problem.

 

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
system_rgb2dvi_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

 

 

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I deleted the offending Ethernet code and downloaded the newly created file to the board.

Unfortunately Displayport does not work.

Can't receive a file that is confirmed?

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Hi @chunho ok,

As mentioned in the thread that @Ana-Maria Balas linked to, the Displayport doesn't work in the posted demo because an extra license file is required which each individual user would need to pay for on their own, though the configuration that is provided on Genesys 2 at the factory does work. It is possible to port XAPP1178 files to the design, though the material that the user posted does not appear to still be available for download.

Thanks,
JColvin

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IP license is no problem.

If you reload the SDK (Microblaze) file while the genesys2 board demo is running, Displayport is not displayed.

Is not a problem with the SDK file ??

4444.JPG

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Hi @chunho ok,

I apologize for the delay. My understanding is that it the displayport IP is not the entire issue (though it does not help the situation). More specifically, it seems that the newer versions DisplayPort IP that were published after the OOB project was designed require a particular retimer, a TI DP159 retimer, the IC of which is not part of the Genesys 2 design. It is possible to create material to properly pass the data from vdma and DDR to the DisplayPort without using the IP itself, though Digilent has not done this.

Thanks,
JColvin

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Hi @chunho ok,

It took me a while, but I found on our servers the original project for Genesys 2 OOB, which was made with Vivado 2014.4.

With the next release of Vivado (Vivado 2015.4) Xilinx made some changes to the DisplayPort IP and that is why the Display Port doesn't work in Vivado 2015.4.

For the moment I'm caught in some work and I don't have time to test the project sources and see that everything works, but I'll put here the sources for you to test them, otherwise you'll have to wait around 3 weeks until I have time to test them.

Download Vivado 2014.4 and below are the demo sources:

G2demo.zip

 

 

Edited by Ana-Maria Balas

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