ISERDESE2 correct implementation

[ashura]

Hello to all,

I am trying to receive an LVDS signal (clk and data) and when I tried to implement the serial to parallel block (ISERDESE2) the output always X. Below is the instantiation I am using with all the parameters. I am trying to follow the document below and I am stuck with the deserialize. If there is a mistake in the code below can you please identify it. Also, if you have any suggestions to use different deserialize or other way to implement LVDS signal receiver please let me know. 

 

ISERDESE2_inst : ISERDESE2 
    generic map (
        DATA_RATE => "DDR",           -- DDR, SDR  
        DATA_WIDTH => 8,              -- Parallel data width (2-8,10,14)      
        DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)  
        DYN_CLK_INV_EN => "FALSE",    -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)   
        -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)   
        INIT_Q1 => '0',   
        INIT_Q2 => '0',   
        INIT_Q3 => '0',   
        INIT_Q4 => '0',   
        INTERFACE_TYPE => "NETWORKING",   -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE   
        IOBDELAY => "NONE",           -- NONE, BOTH, IBUF, IFD   
        NUM_CE => 2,                  -- Number of clock enables (1,2)   
        OFB_USED => "FALSE",          -- Select OFB path (FALSE, TRUE)   
        SERDES_MODE => "MASTER",      -- MASTER, SLAVE   
        -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)   
        SRVAL_Q1 => '0',   
        SRVAL_Q2 => '0',
        SRVAL_Q3 => '0',   
        SRVAL_Q4 => '0' 
    ) 
    port map (
        O => data_out,                       -- 1-bit output: Combinatorial output   
        -- Q1 - Q8: 1-bit (each) output: Registered data outputs   
        Q1 => Q1,   
        Q2 => Q2,   
        Q3 => Q3,   
        Q4 => Q4,   
        Q5 => Q5,   
        Q6 => Q6,   
        Q7 => Q7,   
        Q8 => Q8,   
        -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports   
        SHIFTOUT1 => SHIFTOUT1,   
        SHIFTOUT2 => SHIFTOUT2,   
        BITSLIP => HIGH,             -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to                                 
                        -- CLKDIV when asserted (active High). Subsequently, the data seen on the                                 
                        -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one                                 
                        -- position every time Bitslip is invoked (DDR operation is different from                                 
                        -- SDR).
        -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs   
        CE1 => '1',   
        CE2 => '1',   
        CLKDIVP => '0',           -- 1-bit input: TBD   
        -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports   
        CLK => clk,                   -- 1-bit input: High-speed clock   
        CLKB => CLKB,                 -- 1-bit input: High-speed secondary clock   
        CLKDIV => clk_div,             -- 1-bit input: Divided clock   
        OCLK => '0',                 -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"   
        -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity   
        DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion   
        DYNCLKSEL => '0',       -- 1-bit input: Dynamic CLK/CLKB inversion   
        -- Input Data: 1-bit (each) input: ISERDESE2 data input ports   
        D => data_in,                       -- 1-bit input: Data input   
        DDLY => '0',                 -- 1-bit input: Serial data from IDELAYE2   
        OFB => '0',                   -- 1-bit input: Data feedback from OSERDESE2   
        OCLKB => '0',               -- 1-bit input: High speed negative edge output clock   
        RST => '0',                   -- 1-bit input: Active high asynchronous reset   
        -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports   
        SHIFTIN1 => '0',   
        SHIFTIN2 =>'0' 
    ); 

The doc I am following.

https://www.xilinx.com/support/documentation/application_notes/xapp1017-lvds-ddr-deserial.pdf

 

Thank you in advance.

[ashura]

It seem there is no answer so I will delete the question.

[eric Qiang]

How do you solve this issue? I have been stucken in here for a long time.