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Error creating Vivado project for ZMOD ADC and DAC on Eclypse board


Paul Chang

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Dear Sir,

I would like to re-create the zmod_adc_dac vivado project.

 I have follow this link 

Quote

The Vivado project must be recreated from its source before being able to be opened. To create the project, first open the supported version of Vivado1). Open Vivado's TCL console, and enter the command below. This will recreate and open the Vivado project.

set argv ""; source <local repo>/hw/digilent-vivado-scripts/digilent_vivado_checkout.tcl

But it seems can not  recreate the Vivado project. 

Error below: (more info and please see log.txt)

can't read "assoc": no such variable
ERROR: [BD 41-1273] Error running post_config_ip TCL procedure: can't read "assoc": no such variable
    update_assoc_busif Line 6

 

Best Regards,

Paul 

error.png

log.txt

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8 answers to this question

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Hello,

You should be able to run the Baremetal ADC and DAC demos from Windows. 

First of all, you don't need to create the Vivado project in order to run these demos, as the provided SDK workspace contains the exported handoff file:

  • download the provided SDK workspace  
Quote

git clone --recursive https://github.com/Digilent/Eclypse-Z7-SW.git -b zmod_adc_dac/master

  • in SDK Environment import the projects from the downloaded location
  • program the FPGA using the design_1_wrapper.bit file from the in the design_1_wrapper_hw_platform_0 folder 
  • you should be able to run the ZmodADC1410_Demo_Baremetal and ZmodDAC1411_Demo_Baremetal demos (eventually recreating the bsp sources in the corresponding bsp projects) 

Still, if you want to create the Vivado project, it is available on this location:

Quote

git clone --recursive https://github.com/Digilent/Eclypse-Z7-HW.git -b zmod_adc_dac/master

I was able to create the project using the instructions linked from github project readme.

The block design looks like this:

 image.thumb.png.2c66dcfb451d8c193da3b553012735d6.png

Regarding my previous post, please ignore my advice to remove .Xilinx directory. You should only remove .Xil directory, if exists.

Please tell me if you still encounter issues with these demos.

Best Regards,

Cristian 

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Hi Cristian ,

Thanks for your support.

I don't know why I can not success to create the vivado project.

Please see my process:

1.  git clone --recursive https://github.com/Digilent/Eclypse-Z7-HW.git -b zmod_adc_dac/master

2. open vivado 2019.1

3. type below command in tcl window

Quote

set argv ""; source D:/Eclypse-Z7-HW/digilent-vivado-scripts/digilent_vivado_checkout.tcl 

4. The error is same. 

error.thumb.png.b74a6f28a055c02fcf98859b30d1a694.png

 

Best Regards,

Paul

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@Paul Chang

I haven't managed to reproduce this yet. For what it's worth, I also use a Windows 10 system. Thanks for posting the log file.

According to this Xilinx Forum thread, there may be some strange issues relating to the AXI SmartConnect that depend on system settings.

I have a couple of ideas for things that we could try to work around it.

1. I've attached an archived version of the project, which I checked out on my machine.

2. If (1) doesn't work, it may be necessary to replace the AXI SmartConnect with an AXI Interconnect. This could get a bit complicated, and I am looking into it.

Thanks,

Arthur

Eclypse-Z7-HW.xpr.zip

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@Paul Chang

I can confirm that you are using the correct flow to get the project. There aren't any licensing concerns around either the smartconnect or fifo generator IPs. I may be able to get some more information from the errors in the third image (Windows 10), if you expand the [IP Flow 19-167] error, or if you upload a log file for that project. However, since each of the errors that show up in your screenshots appear to be related to files inside of the Xilinx installation directory, I'd recommend that you reach out to them on their Forums.

Apologies,

Arthur

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