Accessing the DDR2 memory from two different components

[noureddine-as]

Hi,

I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR  (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface.

Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?

[zygot]

22 hours ago, noureddine-as said:

I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?

One of the nifty features of the Spartan 6 family was the multi-channel external memory controller hard logic block. I've used 2 or more channels with a round-robin access scheme for many a design. Some FPGA devices have hard memory controllers and some, like Artix,  rely on all-programmable logic external memory controllers. I don't use MicroBlaze so I'm unfamiliar with it's AXI external memory controller so I don't know if you can DMA data into the DDR.

Since audio sample rates are relatively low you might want to just allocate some of your soft-processor bandwidth to maintaining a circular buffer in DDR memory. If that doesn't work you could explore other storage media such as an SD card.

[asmi]

On 2/4/2020 at 9:33 AM, noureddine-as said:

Hi,

I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR  (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface.

Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?

What do you mean by "interface is taken by the processor"? You connect your memory controller to a master port of AXI Interconnect (or AXI SmartConnect), then connect any amount of masters to the slave ports of that interconnect. This way any master can access any location of a memory, you will only need to watch out for race conditions (when several masters are trying to access the same memory location at the same time), also if you CPU has data cache, you will need to flush it to ensure other masters can "see" the changes made by CPU. All arbitration is handled by the interconnect, and you can configure it to your liking (like giving some master priority over others).