I understand quite a few things have changed with the SDK to Vitis migration on the software side. But, I am having trouble with the hardware also
I followed this tutorial and I get two error while trying to generate bitstream https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start
Any help is greatly appreciated. Thanks in advance
The error message is as follows -
[BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_microblaze_0_0
system_axi_gpio_input_0
system_axi_gpio_led_0
system_mdm_1_0
system_axi_uartlite_0_0
system_axi_quad_spi_0_0
system_axi_smc_0
system_clk_wiz_0_0
system_ilmb_bram_if_cntlr_0
system_axi_timer_0_0
system_microblaze_0_axi_intc_0
system_microblaze_0_axi_periph_0
system_microblaze_0_xlconcat_0
system_mig_7series_0_0
system_rst_clk_wiz_0_100M_0
system_rst_mig_7series_0_81M_0
system_xadc_wiz_0_0
system_dlmb_bram_if_cntlr_0
system_dlmb_v10_0
system_ilmb_v10_0
system_lmb_bram_0
system_xbar_0
[Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]).
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Vik
I understand quite a few things have changed with the SDK to Vitis migration on the software side. But, I am having trouble with the hardware also
I followed this tutorial and I get two error while trying to generate bitstream https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start
Any help is greatly appreciated. Thanks in advance
The error message is as follows -
[BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_microblaze_0_0
system_axi_gpio_input_0
system_axi_gpio_led_0
system_mdm_1_0
system_axi_uartlite_0_0
system_axi_quad_spi_0_0
system_axi_smc_0
system_clk_wiz_0_0
system_ilmb_bram_if_cntlr_0
system_axi_timer_0_0
system_microblaze_0_axi_intc_0
system_microblaze_0_axi_periph_0
system_microblaze_0_xlconcat_0
system_mig_7series_0_0
system_rst_clk_wiz_0_100M_0
system_rst_mig_7series_0_81M_0
system_xadc_wiz_0_0
system_dlmb_bram_if_cntlr_0
system_dlmb_v10_0
system_ilmb_v10_0
system_lmb_bram_0
system_xbar_0
[Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]).
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