Output Problem when conncet Own IP to Zynq IP in Block Design

[satvik]

Hello everyone,

I am working on CoraZ0S Zynq Block design with Pmod DAC. I successfully run my SPI Verilog interface for Pmod DAC and i got ramp up signal from Pmod DAC. I make IP core from that code. I started new block design and add only my SPI IP core for Pmod DAC and make clock and output as extern and assign pin and run on my board again it give ramp up signal.

I want to connect my IP core with ZYNQ SOC IP core because I want to get data from ARM whichi will pass to PmodDAC via my SPI IP core. I add ZYNQ ip core and connect my SPI IP core clock signal to FCLK_0(set to 100Mhz) of ZYNQ IP core and rest of left as it is.

Then I generate bit/ bin file and load on my board but there is no output form Pmod DAC. After that i generate test bench and in simulation output is apear from my SPI IP core. Then why no output when i load onto FPGA board. 

Is there any mistake i did or i miss any step?

Thansk in advance.

[Ana-Maria Balas]

Hello @satvik,

For now I think that maybe you should create an AXI Peripheral IP so that the Zynq can control the IP and also a memory address for that IP will be allocated ( you can check if your IP have a memory address by pressing the Address Editor Tab in Vivado Design)

Here is a link with a tutorial from Xilinx which explains how to create an AXI Peripheral IP.

The tutorial from Xilinx doesn't give you enough directions, you should make a little research.

Here is a tutorial from Digilent which is quite simple: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start

Also some Youtube videos which will help you understand the AXI Peripheral IPs:

https://www.youtube.com/watch?v=meQcwzC4Vtk

https://www.youtube.com/watch?v=Vs0h0kue7p4

 

 

[satvik]

Hello @Ana-Maria Balas

Thank you so much for your reply and  i am happy to say that i got sollution for my problem.

i got the actual problem in my case is, i connected my IP core to Zynq SOC clock out (FCLK_CLK0) but i was uploading the bit file from vivado Hardware Manager and expect to get output without running any application form SDK. 

When i run application from SDK then only the  FCLK_CLK0 give clock out and my own IP core(PmodDAC2) give me output. Now same thing happen with custom axi ip core and i got my problem solved.

Thank you for your suggestions. I have gone throgh all links that you provided and it is quit helpfull to me.