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Getting Started with Microblaze Servers on Nexys A7 - error


Michal Hucik

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Hi,

I'm trying to reproduce tutorial Nexys 4 DDR - Getting Started with Microblaze Servers for my Nexys A7. I have included the Nexys A7 board definitions in the Vivado. When I try the Generate Bitstream, so I receive these error messages:

Implementation -> Write Bitstream -> DRC -> Pin Planning:

[DRC NSTD-1] Unspecified I/O Standard: 15 out of 71 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
 

[DRC UCIO-1] Unconstrained Logical Port: 15 out of 71 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
 

They are ok board pinout definitions? How to correctly fix this problem?

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Hi @Michal Hucik,

I'm not certain version of Vivado you are attempting to use (I believe you are using the -100T version), but I went through the guide in Vivado 2018.2 and was able to successfully generate the bitstream for the Nexys A7.

I also wanted to confirm with you is that you used the Digilent Board files to select the Nexys A7. Could you also attach your Block Design? You can get a clean visual of it by right clicking in the blank space and selecting "Save as PDF file".

Thanks,
JColvin

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Hi,
I'm running the Vivado 2018.2 and I use Nexys A7-100.
I try to reproduce this tutorial https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start

I'm discover that i have not connected AXI EthernetLite MII output into Ethernet PHY input and activation the Connection Automation caused,  so the MII output pin is now connected as "mii_rtl" output.
After fix this problem I can generate the bitstream without errors.
Thank you for help the move to next stage.

However in another step I encountered a another problem, this time in  the SDK.

In the point 8.2 I create a new application project with the lwIP Echo Server templates. Project is created, but auto compilation of echo_server_bsp generates a several errors - see screenshot.
The lwip library is not prepared and the echo_server application can't be compiled:

mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../echo_server_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "echo_server.elf"  ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: cannot find -llwip4
collect2.exe: error: ld returned 1 exit status
make: *** [echo_server.elf] Error 1

sdk_lwip_error.png

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Hi @Michal Hucik,

I recieved the same error in SDK as well. I'm not certain what the issue is, though I did notice that the lwip library is updated/different from the tutorial, so I am not certain if that introduces a different change that needs to be accounted for. I know that in Vivado & SDK 2017.4 it is still on the lwip141 library version that is mentioned in the tutorial, so I am attempting to go through the tutorial in that version as well as a later 2019.2 version in case there is some sort of issue with 2018.2 that I am not aware of, but creating the two bitstreams is taking longer than I anticipated, but I will let you know the results of what I found when the projects finish.

Thanks,
JColvin

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Hi @Michal Hucik,

Later versions of Vivado will not readily work as the MII to RMII IP core is no longer included with Vivado and as per this Xilinx forum thread, there is no recommended replacement available, so we don't currently have any recommendations for this material later versions of Vivado with non-Zynq chips.

I was able to confirm that both Vivado and SDK work with this material on the 2017.4 versions though.

Let me know if you have any questions about this.

Thanks,
JColvin

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Hi,
thank You for message.

I thing so I have now solution for the Vivado 2018.2 because I found this patch https://www.xilinx.com/support/answers/71330.html
Line numbers in patch file are different from my version of xadapter.c, but is not problem found correct places in the source file echo_server_bsp/microblaze_0/libsrc/lwip202_v1_1/src/contrib/ports/xilinx/netif/xadapter.c 
My new version xadapter.c is in the attachment.

Regards, Michal Hucik

xadapter.c

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