I'm trying to reproduce tutorial Nexys 4 DDR - Getting Started with Microblaze Servers for my Nexys A7. I have included the Nexys A7 board definitions in the Vivado. When I try the Generate Bitstream, so I receive these error messages:
[DRC NSTD-1] Unspecified I/O Standard: 15 out of 71 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
[DRC UCIO-1] Unconstrained Logical Port: 15 out of 71 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
They are ok board pinout definitions? How to correctly fix this problem?
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Michal Hucik
Hi,
I'm trying to reproduce tutorial Nexys 4 DDR - Getting Started with Microblaze Servers for my Nexys A7. I have included the Nexys A7 board definitions in the Vivado. When I try the Generate Bitstream, so I receive these error messages:
Implementation -> Write Bitstream -> DRC -> Pin Planning:
[DRC NSTD-1] Unspecified I/O Standard: 15 out of 71 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
[DRC UCIO-1] Unconstrained Logical Port: 15 out of 71 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en.
They are ok board pinout definitions? How to correctly fix this problem?
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