Questions through an example of a verilog (binary counter)

[infpgaadv]

Hi, I try to learn verilog. There are a few things I don't understand about the following code(2., which is long.). I would appreciate if you help.

Not: I'm a vhdl user

1-)What is the purpose of the always block used here?

2-) "assign count_next = count_reg + 1; // increase the count "  how work this piece of code? Isn't it expected to grow rapidly by adding one? without stopping. How and when does count_next and count_reg get the new value?

3-)I would write something like this;

// this is my code

module counter (clk, reset, count);
    input clk, reset;
    output [3:0] count;
    reg [3:0] count;
    always @(posedge clk or posedge reset )
         if (reset) 
              count <= 4'b0000;
         else
               count <= count + 1'b1;
endmodule

-----------------------------------------------

 

module binaryCounter
#(
    parameter N = 3 //N bit binary counter
)
(
    input wire clk, reset, 
    output wire complete_tick, 
    output wire[N-1:0] count
);

localparam MAX_COUNT = 2**N-1; // maximum value for N-bit

reg[N-1:0] count_reg;
wire[N-1:0] count_next;

always @(posedge clk, posedge reset)
begin
    if (reset == 1)
        count_reg <= 0;  // set count to 0 if reset
    else
        count_reg <= count_next; // assign next value of count
end

assign count_next = count_reg + 1;  // increase the count

// generate tick on each maximum count 
assign complete_tick = (count_reg == MAX_COUNT) ? 1 : 0;

assign count = count_reg; // assign value to output port

endmodule

[xc6lx45]

Hi,

you can search for the keyword "blocking" vs "non-blocking" assignment in Verilog. You can get a hint at the answer (also the "always @(posedge clk) if you look at the schematic in your post. Note the triangle, "C" is an edge sensitive input (which goes down to the transistor level electronics that ultimately define the foundations of "synchronous" logic design as we know it). This only as sneak preview to what a web search will reveal ?