Jump to content
  • 0

Decoupling Configuring the FPGA and Loading Software with a ZedBoard


JohnA.

Question

I am looking for the best way to decouple configuring the FPGA on my ZedBoard from loading and booting the software.  The catch is, I need to be able to configure the FPGA with an SVF file through the standard JTAG port and *not* the USB JTAG port.  The software I am somewhat flexible on loading an booting after the FPGA is configured, but it would need to *not* involve the USB JTAG as well, as I am afraid their might be a conflict between the two JTAG ports.  Thanks in advance!

Link to comment
Share on other sites

9 answers to this question

Recommended Posts

Hi @JohnA.,

I'm not certain why you need to decouple to two JTAG ports (since the UART port is separated from the programming port or if there is a different reason), but if you use something like the JTAG HS3, you can then use the Digilent Adept software to load the .svf file to the downstream Zynq SoC.

Let me know if this is not what you are looking for.

Thanks,
JColvin

Link to comment
Share on other sites

Hi JColvin,

 

Thanks for the prompt reply.

We have a software tool to load the SVF into the FPGA by way of the standard JTAG port.  What's got me tripped up is, after I get the FPGA loaded, I can't figure out how to get the software loaded and booted.  Attempts to do so by way of the QSPI and the the USB JTAG produce an error that I believe comes down to the fact that I am using the standard JTAG port to load with the FPGA.  I have attached the error message I receive.

I've experimented with moving jumpers and even disconnecting the JTAG cable after I load the FPGA, but I haven't found the right solution.  Is there a way to load the software through the PC UART USB? 

Thanks!

 

ErrorMessage.docx

Link to comment
Share on other sites

Hi @JohnA.,

I don't have ISE available to directly test this (since I'm on Windows 10), but on Vivado and SDK, I was able to to successfully load the .bit file and the application project launched. If I have a second USB cable attached to the PROG port (J17), then I am not able to readily choose to load the application.

I don't know what tool you are using to load the file via the standard JTAG board, but do you happen to know if the tool you are using as the capability to drive the PS_SRST_B low? Xilinx tools occasionally require the processor core to be reset during debug operations (of which launching on hardware (system debugger)).

As an additional question, what version of the Zedboard do you have and how are the mode jumpers configured on it (I realize you tried a number of options already, but in the interest of being on the same page.

I do not think there is a way to load it through the UART USB as it is not connected to the necessary programming lines.

Thanks,
JColvin

 

Link to comment
Share on other sites

Hi JColvin,

The company I work for, ASSET-InterTech, is in the business of Boundary Scan software and hardware for testing boards and ICs.  We interface with devices through their JTAG ports.  I think the debugger being in the boundary scan chain is definitely an element.  I am not sure if we could reach the PS_SRST_B signal, unless it is reachable through the JTAG chain somehow.

According to the documentation that came with the ZedBoard, it's version 1.1 with the XC7Z020-1CSG484CES FPGA.  I've attached images showing my board setup and the positions of the jumpers--it's the configuration I use that enables me to get the FPGA loaded.

And, just to be sure, its the software I was wandering if could be loaded and booted via the PS UART.  But loading it and booting it from QSPI, or SD card would do just as well.

 

 

Jumpers.jpg

TheBoard.jpg

Link to comment
Share on other sites

Hi @JohnA.,

The PS_SRST_B is available on the JTAG header on pin 14; there is a reference image showing where it is on the Xilinx JTAG header on the JTAG HS3 reference manual here: https://reference.digilentinc.com/jtag_hs3/refmanual#xilinx_zynq-7000_and_soc_support.

I think for the jumpers you will need to change MIO2, as per the the Zedboard User Guide (pg 28) the current setting puts it in Independent JTAG mode which as per AR# 47599 from Xilinx the PS on a Zynq chip cannot be accessed through the ARM DAP which is affected by the CES chip versions. Could you try setting this value to be in Cascaded JTAG (settings the signal to ground)?

Thanks,
JColvin

Link to comment
Share on other sites

Hi JColvin,

Okay, setting MIO2 to cascaded mode and a tweak to our SVF file did the trick!  I am nor loading the FPGA via the standard JTAG port and loading and booting the software via the USB JTAG.  Thanks a lot for your help, I really appreciate it!

 

Link to comment
Share on other sites

On 1/17/2020 at 4:19 PM, JColvin said:

I don't have ISE available to directly test this (since I'm on Windows 10)

I was stumped trying to run ISE on Win10 for a while but have had it working for a few months.

  1. Install the October 2013 final release of ISE 14.7, not the later December release ( the latter doesn't support Spartan 3A)
  2. Read AR# 62380 for post-install steps to disable SmartHeap and get it working.

I've built and configured (using the Windows Adept Utility) a few Spartan 6 boards with ISE on Win10. I haven't exercised all of the ISE tools but haven't had to so far.

Link to comment
Share on other sites

Hi @zygot,

I guess to amend my statement, I do have the Windows 10 December version of ISE installed, but unfortunately that version does not support Zynq chips, hence why I said I didn't have ISE available to test this (by which I meant loading a .svf file since I didn't have one available as a test to load). I will look into the AR# 62380 though for those post install steps to get the October version working though.

Thanks for the tip.

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...