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Tim S.

set_input_delay set_output_delay for AXI block


After synthesizing an AXI block diagram with Microblaze for the Arty-A7-100T, I am aware that the timing report shows that input and output ports at the board interface are not constrained with input and output delays. (set_input_delay , set_output_delay). Vivado indicates these omissions to be of high severity.

To apply these constraints in an XDC, it is necessary to know which clock of the internal clocks registers the inputs and outputs on these pins, so that the specified delay can include this information in the XDC. Where do I start, for determining the associated clock signal and name?


Tim S.

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