• 0
Tim S.

set_input_delay set_output_delay for AXI block

Question

After synthesizing an AXI block diagram with Microblaze for the Arty-A7-100T, I am aware that the timing report shows that input and output ports at the board interface are not constrained with input and output delays. (set_input_delay , set_output_delay). Vivado indicates these omissions to be of high severity.

To apply these constraints in an XDC, it is necessary to know which clock of the internal clocks registers the inputs and outputs on these pins, so that the specified delay can include this information in the XDC. Where do I start, for determining the associated clock signal and name?

Regards,

Tim S.

Share this post


Link to post
Share on other sites

0 answers to this question

Recommended Posts

There have been no answers to this question yet

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now