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xc6lx45

Public service announcement: PLL locking

Question

"Due to recent events":

Please be aware that by default, the FPGA (Xilinx 7 series) wakes up with PLLs possibly still unlocked. This is explicitly stated in UG908 p. 70 and shouldn't surprise anyone who has read the manual 🙂 See "BITSTREAM.STARTUP.LCK_CYCLE" option.

"Recent events" means that yesterday, I found that my design (which started from the first clock cycle), worked 100 % reliably on one board but failed with 100 % certainty on the other board. Identical RTL with initial delay in SW did work reliably on both boards so this is a shy little bug ...

Adding simple reset logic based on the .locked signals from the PLLs solved the issue, now both boards are functional.

 

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You can force config logic to wait for PLL/MCMM locks before GSR deassertion and design startup. RTFM: UG472 table 3-7, parameter STARTUP_WAIT. But you've got to be careful with this option as design will never start if one of clocks is not present at startup - typical case being HDMI input, or just about any non-MGT high-speed input for that matter. So it's fine to use it for system clock(s), but it's a definitely "NO" for IO clocks.

Edited by asmi

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12 hours ago, xc6lx45 said:

Adding simple reset logic based on the .locked signals from the PLLs solved the issue, now both boards are functional.

You knew that there was a reason for this MMCM or PLL output right?

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3 hours ago, xc6lx45 said:

Yes but I had already proven that it works

Well that brought a chuckle to my completely humorless day. Reality is so inconvenient... there must be a way to get along without it. Corporate officers do SOP. Accountants just make the books more complicated to avoid it.

Simulating 100 us or so of nothing waiting for an MMCM to lock is annoying enough to sear the question of start-up into one's mental sensitivity list. I've never tried simulating configuration start-up though... still simulating has pointed out more than a few 'oversights' in my preparation on many an occasion.

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