Please be aware that by default, the FPGA (Xilinx 7 series) wakes up with PLLs possibly still unlocked. This is explicitly stated in UG908 p. 70 and shouldn't surprise anyone who has read the manual ? See "BITSTREAM.STARTUP.LCK_CYCLE" option.
"Recent events" means that yesterday, I found that my design (which started from the first clock cycle), worked 100 % reliably on one board but failed with 100 % certainty on the other board. Identical RTL with initial delay in SW did work reliably on both boards so this is a shy little bug ...
Adding simple reset logic based on the .locked signals from the PLLs solved the issue, now both boards are functional.
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"Due to recent events":
Please be aware that by default, the FPGA (Xilinx 7 series) wakes up with PLLs possibly still unlocked. This is explicitly stated in UG908 p. 70 and shouldn't surprise anyone who has read the manual ? See "BITSTREAM.STARTUP.LCK_CYCLE" option.
"Recent events" means that yesterday, I found that my design (which started from the first clock cycle), worked 100 % reliably on one board but failed with 100 % certainty on the other board. Identical RTL with initial delay in SW did work reliably on both boards so this is a shy little bug ...
Adding simple reset logic based on the .locked signals from the PLLs solved the issue, now both boards are functional.
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