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Setting the Internal reference on PMOD DA4


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I am interfacing to the PMOD Da4 with the ARTY4 A7.  I wrote Verilog to write the internal reference register to enable the internal reference  right after power up.  The internal reference voltage never gets turned on.   Attached is the simulation in Vivado which look just like the logic analyzer of the signals.  Is there a minimum amount of time that I need to wait after power up for the reference voltage to work?    My next thing I was going to try is to slow down the SCLK, but it looks like it meets all timing to me at 50MHz 

Or maybe I need to send a reset command on power up before setting the Internal reference?  I had this problems with a Maxim ADC in the past, it needed a reset to work correctly because of a bug in the internal reset circuit.  

 

 

thanks

PMOD-DA4_Vref sim.PNG

Edited by mladenik
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I think so, But that is why I attached the bit stream that gets sent to the device on power up. Data changes from the FPGA on the rising edge to be clocked into the DAC on the Falling edge.  The data stream is 32 bits hex value 080001h as indicated in the data sheet as the value needed to enable the internal reference.  The 8 is the internal reference setup command and the 1 is the internal ref enable as shown in table 12 of the AD5628 data sheet.  And timing is close but seems to meet the timing. 

but I will triple check these things when I get into work this morning.  I’m thinking of halving the frequency to 25mhz and also sending a reset command on power up before the internal reference enable command to see if that changes anything.   

Thanks for the response. 

 

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The hexa value is 08000001h  not 080001h for the input register to set the internal ref. The Pmod DA4 comunicates over SPI mode 3.

From your simulation I see that the mode is mode 2. The data is available on the falling edge of SCLK.

Below is a diagram that can help you understand:

image.thumb.png.289a00a44e018afe0c481f67b69bdfc6.png

image.thumb.png.8f15ae0e30dd61d086d15e84da1f454a.png

For mode 3, you want the data to be available on the leading edge not on the falling edge of SCLK.

 

 

Edited by Ana-Maria Balas
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OK I am probably missing something

Yes Mode 2 falling edge because the AD5628 data sheet says that the date in shifted into the DAC on the falling edge. See below the verbage and timing diagram from the data sheet and the timing diagram.  You can see the setup and hold times t5 & t6 given are from the falling edge of the SCLK.  
 

From data sheet
"Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK."  

 

and

 

"On the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation."

image.png.fc812dfb41b800a530011654171893e8.png

image.png.76af140c1bc4e4ea86264f7bad3ebeed.png

 

 

And the value according to the data sheet should be the value that I am sending in the timing diagram.   

image.thumb.png.a0470f47da714a0d6855d47ba7d34fee.png

Bits DB[31:28] = 0

Bits DB[27:24] = 8

Bits 23-1 = 0 (or don't cares) DB[23:4] = 000

Bit 0 =1  DB[3-0] = 1

which is 08000001h  which is what my data stream below shows. I left some zeroes out in my previous text sorry)  32 clock edges with a 1 in DB27 and DB0 as table 1 shows.  If this is not correct what should the 32 bit word be?     

 

image.thumb.png.feb15635f2a59a4cc8f6162c734afb53.png

 

Am I looking at the wrong data sheet or interpreting something wrong?     Why do you think it should be rising edge and what 32 bit word should I be writing in order to turn the internal reference on?  

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My timing diagram and AD5628 timing diagram both show the data is shifted out of the master on rising but into the DAC on the falling with the falling edge in the center of the bit.  setup and hold from falling edge must be min 4ns each and the 50MHz clock means 10ns for each.    Do you think the rising edge should be in the center of the bit?  

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What SCLK rate are you using with the Microblaze?   Do you see how that violates the Data sheet spec for the AD5628 and will insure that the setup and hold times are not being met?  I am sure that will work on a slow SCLK but will definitely violate the setup and hold for a 50MHz SCLK. 

 

I think I found the issue,  I downloaded the fixed version in RAM and not into the FLASH so it kept loading the old code and not the new code.  

 

thanks for your help. 

 

 

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To clarify, the Microblaze clock was set to 100Mhz, and the Axi Quad SPI used the default internal frequency ratio, which I think is 16, so I got a SCLK frequency of around 6 Mhz.

But you say that you fixed it, and I want to know which mode did you use and it's working properly with Pmod DA4? 

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Mode 2 as described in the AD5628 spec.  I am 100% sure if you change to mode 2 it will work for you too.   And I would not be surprised if you increase the SCLK to 50MHz with MODE 3 you will have problems.  

Thanks  again for the help 

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