I am using the Basys3 board, Vicado 2019.1, and verilog as a "new learner" in an attempt to implement an alarm clock found on the web. I am unclear as to how to set up the clock in the xdc file
My source module file...
module aclock (
input clock_100Mhz,// 100 Mhz clock source on Basys 3 FPGA
input reset, // sw0 Active high reset pulse, to set the time to the input hour and minute.
// (as defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00.
// It should also set the alarm value to 0.00.00, and to set the Alarm (output) low.
// For normal operation, this input pin should be 0.
input [1:0] H_in1, // sw15,14 A 2-bit input used to set the most significant hour digit of the clock
// (if LD_time=1),or the most significant hour digit of the alarm (if LD_alarm=1).
// Valid values are 0 to 2.
input [3:0] H_in0, // sw 13,12,11,10 A 4-bit input used to set the least significant hour digit of the clock
// (if LD_time=1),or the least significant hour digit of the alarm (if LD_alarm=1).
// Valid values are 0 to 9.
input [3:0] M_in1, // sw9,8,7,6 A 4-bit input to set the most significant min digit of the clock (if LD_time=1)
// or the most significant min digit of the alarm (if LD_alarm=1). Valid values are 0 to 5.
input [3:0] M_in0, // sw5,4,3,2 A 4-bit input to set the least significant min digit of the clock (if LD_time=1),
// or the least significant min digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.
input LD_time, // sw-LT If LD_time=1, the time should be set to the values on the inputs H_in1, H_in0, M_in1,
// and M_in0. The second time should be set to 0.If LD_time=0, the clock should act
// normally (i.e. second should be incremented every 10 clock cycles).
input LD_alarm, // sw-RT If LD_alarm=1, the alarm time should be set to the values on the inputs H_in1,
// H_in0, M_in1, and M_in0.If LD_alarm=0, the clock should act normally.
input STOP_al, // sw-CEN If the Alarm (output) is high, then STOP_al=1 will bring the output back low. */
input AL_ON, // sw-0 If high, the alarm is ON (and Alarm will go high if the alarm time equals the real time).
// If low the the alarm function is OFF. */
The question. Is this the right way to sub the clock into the xdc file? The clock part of the xdc file follows...
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
I'm not sure if all three lines need the clock_100Mhz substitute. The "clock" display and alarm works and vicado generated no errors, but it doesn't count.
Question
techy5025
I am using the Basys3 board, Vicado 2019.1, and verilog as a "new learner" in an attempt to implement an alarm clock found on the web. I am unclear as to how to set up the clock in the xdc file
My source module file...
module aclock (
input clock_100Mhz,// 100 Mhz clock source on Basys 3 FPGA
input reset, // sw0 Active high reset pulse, to set the time to the input hour and minute.
// (as defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00.
// It should also set the alarm value to 0.00.00, and to set the Alarm (output) low.
// For normal operation, this input pin should be 0.
input [1:0] H_in1, // sw15,14 A 2-bit input used to set the most significant hour digit of the clock
// (if LD_time=1),or the most significant hour digit of the alarm (if LD_alarm=1).
// Valid values are 0 to 2.
input [3:0] H_in0, // sw 13,12,11,10 A 4-bit input used to set the least significant hour digit of the clock
// (if LD_time=1),or the least significant hour digit of the alarm (if LD_alarm=1).
// Valid values are 0 to 9.
input [3:0] M_in1, // sw9,8,7,6 A 4-bit input to set the most significant min digit of the clock (if LD_time=1)
// or the most significant min digit of the alarm (if LD_alarm=1). Valid values are 0 to 5.
input [3:0] M_in0, // sw5,4,3,2 A 4-bit input to set the least significant min digit of the clock (if LD_time=1),
// or the least significant min digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.
input LD_time, // sw-LT If LD_time=1, the time should be set to the values on the inputs H_in1, H_in0, M_in1,
// and M_in0. The second time should be set to 0.If LD_time=0, the clock should act
// normally (i.e. second should be incremented every 10 clock cycles).
input LD_alarm, // sw-RT If LD_alarm=1, the alarm time should be set to the values on the inputs H_in1,
// H_in0, M_in1, and M_in0.If LD_alarm=0, the clock should act normally.
input STOP_al, // sw-CEN If the Alarm (output) is high, then STOP_al=1 will bring the output back low. */
input AL_ON, // sw-0 If high, the alarm is ON (and Alarm will go high if the alarm time equals the real time).
// If low the the alarm function is OFF. */
The question. Is this the right way to sub the clock into the xdc file? The clock part of the xdc file follows...
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clock_100Mhz]
set_property IOSTANDARD LVCMOS33 [get_ports clock_100Mhz]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clock_100Mhz]
I'm not sure if all three lines need the clock_100Mhz substitute. The "clock" display and alarm works and vicado generated no errors, but it doesn't count.
A newby so I appreciate the help!
Jim
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