Vitis

[zygot]

Today I've set a personal high for the number of experimental projects that have ended in failure. Vivado 2019.2 and Vitis. Need I say more? Well, not all of the misery was trying to combine the two tools.

Vitis currently supports only a handful of platforms. It doesn't support my ZCU106  ( but does support the ZCU104 ). In theory, Vitis supports the Zedboard. Digilent sells the Zedboard. Has anyone had success with Vitis and the Zedboard?

I started with the provided zed XSA file in an attempt at simplifying things. I tried creating a platform with it for both the standalone and RTOS environments. In both cases while trying to create an application the build failed because I didn't have the necessary libraries.  In both cases any attempt to add the necessary libraries by changing the BSP settings resulted in build errors.

Anyone building a working design using Vitas? I really need a win before the day ends,,,,

 

 

[JColvin]

Hi @zygot,

I was able to get a Zedboard project running successfully on Vitis in with a standalone OS, though I had to fight with Vitis for awhile. I will post the project and let you know what I did a bit later this evening (I have to go pick up family from work/daycare right now).

Thanks,
JColvin

[zygot]

@JColvin,

Hey, thanks. For right now I just want a fixed point of reality to hang on to. Where things go after Vivado 2019.1 for ZYNQ can wait. Get on with your life there's no hurry.

[JColvin]

Hi @zygot,

Thanks; I got home and found out that my evening was already scheduled for me.

I have attached the Vitis workspace and the .xsa file I used (the block design I used on the Zedboard was super simple; I used the Digilent board file for the Zedboard with the Pmod GPIO IP block that uses AXI). The rough bit in Vitis was getting the .elf file to be generated within the application project so that I could actually load the project to the Zedboard.

I don't know what the proper procedure is to get it generated (i.e. if you can skip some steps), but what I did was the following:

- Prior to creating the application project, right click on the platform project and selecting "Clean Project" followed by "Build Project"
- Create the application project, clean the application project and then build it by right clicking on it.

This generated the needed .elf; you might still see a problem listed like I do when I confirmed this procedure by creating the Pmod WiFi IP project for the Zedboard where it reports that it can't find the .elf for the FSBL (even though I kept the box unchecked for generating boot components for simplicity's sake), but I was then able to right click, launch on hardware and have the project successfully run.

Let me know if you have any questions and I'll do my best to answer them.

Thanks,
JColvin

design_1_wrapper.xsa vitis_export_archive.ide.zip

[zygot]

@JColvin,

I really appreciate your help. I suspect that I could have had more success by choosing the 'Hello' Application but why bother? I will pursue a Zedboard Vitis project and if it's interesting will post it. It'll be a tertiary level enterprise though.

At this point I've concluded that Vitis and therefore Vivado 2019.2 or later are 'not ready for prime time'. Actually Vivado 2016.2 on WIn7 is my main HDL Xilinx toolset 'main squeeze' and except for a few idiosyncrasies gets the job done. At least I'm familiar with it's quirks. I still can't figure out why implementing a memory viewer in Vivado Simulator is so hard... Quartus has had a hardware memory tool for decades.... ISE ISIM can do it.

A lot of my angst has to do with the knowledge that the Win7 box will die someday and I really haven't found a suitable successor yet. IF only Centos 6 were based on a slightly later Kernel it would be one OS to last (almost) forever.