• 0
Arshi

LVDS input output behaviour

Question

I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal generators  to 1µHz and amplitudes to least  possible value 10mv.  When both the inputs are 10mv, comparator output is zero. I kept analog voltage 10mv and increased reference voltage(51mv) till the comparator turn on. In the next step, reference voltage is kept same and analog voltage is increased till comparator turn on. This process is repeated to max voltage levels.    Please find the attached file for the values noted down. I’m unable to relate this to theory. Analog voltage is always less than Reference voltage but still why the comparator keeps switching? In the beginning its 41mv difference but later it will be 100mv, 250mv …why so?. It would be helpful if someone explain the LVDS input output behavior as a comparator considering those noted values in the file.

 

Comparator_Signalgenerator_inputs 3 copy.xlsx

Share this post


Link to post
Share on other sites

5 answers to this question

Recommended Posts

  • 0
28 minutes ago, Arshi said:

I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS.

@Arshi,

One of us is terribly confused.

Do I understand that you are trying to drive the LVDS_25 input pairs on your Kintex board with a signal generator?

There's no 'analog voltage' and 'reference voltage'. LVDS isn't an analog comparator. LVDS is a differential digital signalling standard where the driver asserts the _n and _p pins to opposite digital levels. The receiver end has to have the proper parallel termination.

If I'm the one who's confused perhaps a better explaination of what it is that you are trying to accomplish might help.

Share this post


Link to post
Share on other sites
  • 0
Posted (edited)

Do I understand that you are trying to drive the LVDS_25 input pairs on your Kintex board with a signal generator?

Yes...

I'm trying to implement Tracking ADC in FPGA. Instead of external comparator, I'm trying to use LVDS as a comparator  Analog and reference voltage is just a naming as mentioned in file. Those are two inputs to LVDS. I'm taking signals from generator to understand LVDS behaviour.

Edited by Arshi

Share this post


Link to post
Share on other sites
  • 0
10 minutes ago, Arshi said:

I'm trying to implement Tracking ADC in FPGA. Instead of external comparator, I'm trying to use LVDS as a comparator

I'm not sure what you mean by Tracking ADC. LVDS has pretty restricted ranges for valid 'analog' levels. Perhaps more verbage would help.

If you are using HR bank IO you need to provide external termination. If you are using HP bank IO you can use internal termination. Either way your receiver must be terminated properly to work. Have you tried driving your input LVDS with an output pair on the same IO bank?

Share this post


Link to post
Share on other sites
  • 0

I understand LVDS cannot be used as a comparator. I have seen in  few papers that LVDS can be used instead of comparator.  Could you please tell me how it works?

Edited by Arshi

Share this post


Link to post
Share on other sites
  • 0
46 minutes ago, Arshi said:

I understand LVDS cannot be used as a comparator. I have seen in  few papers that LVDS can be used instead of comparator.  Could you please tell me how it works?

If you have access to a model or schematic of a discrete logic input, then using it for a purpose that it wasn't design for might be possible. I'd certainly pursue a SPICE simulation as a prototype. ECL is a family that might lend itself to the kind of experimentation that you intend. I have not seen literature about modern FPGA input structures so I wouldn't try and use them for unintended applications.

You can certainly design your own external comparator circuit whose output is compatible with any IOSTANDADs suitable for an FPGA IO Bank IO pin. This would be the safest and most sensible way to proceed. Even if all you want to achieve is some novel design concept, starting with a more traditional approach that's verifiable would seem to be a first step before venturing into the unknown. 

I'm not sure that your concept of tracking ADC is the same as what I think of as a tracking ADC. 

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now