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Arshi

LVDS input output behaviour

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I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal generators  to 1µHz and amplitudes to least  possible value 10mv.  When both the inputs are 10mv, comparator output is zero. I kept analog voltage 10mv and increased reference voltage(51mv) till the comparator turn on. In the next step, reference voltage is kept same and analog voltage is increased till comparator turn on. This process is repeated to max voltage levels.    Please find the attached file for the values noted down. I’m unable to relate this to theory. Analog voltage is always less than Reference voltage but still why the comparator keeps switching? In the beginning its 41mv difference but later it will be 100mv, 250mv …why so?. It would be helpful if someone explain the LVDS input output behavior as a comparator considering those noted values in the file.

 

Comparator_Signalgenerator_inputs 3 copy.xlsx

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28 minutes ago, Arshi said:

I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS.

@Arshi,

One of us is terribly confused.

Do I understand that you are trying to drive the LVDS_25 input pairs on your Kintex board with a signal generator?

There's no 'analog voltage' and 'reference voltage'. LVDS isn't an analog comparator. LVDS is a differential digital signalling standard where the driver asserts the _n and _p pins to opposite digital levels. The receiver end has to have the proper parallel termination.

If I'm the one who's confused perhaps a better explaination of what it is that you are trying to accomplish might help.

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Posted (edited)

Do I understand that you are trying to drive the LVDS_25 input pairs on your Kintex board with a signal generator?

Yes...

I'm trying to implement Tracking ADC in FPGA. Instead of external comparator, I'm trying to use LVDS as a comparator  Analog and reference voltage is just a naming as mentioned in file. Those are two inputs to LVDS. I'm taking signals from generator to understand LVDS behaviour.

Edited by Arshi

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10 minutes ago, Arshi said:

I'm trying to implement Tracking ADC in FPGA. Instead of external comparator, I'm trying to use LVDS as a comparator

I'm not sure what you mean by Tracking ADC. LVDS has pretty restricted ranges for valid 'analog' levels. Perhaps more verbage would help.

If you are using HR bank IO you need to provide external termination. If you are using HP bank IO you can use internal termination. Either way your receiver must be terminated properly to work. Have you tried driving your input LVDS with an output pair on the same IO bank?

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