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AXI DMA not working properly



I have an issue which I really cannot understand. I have a traffic generator connected to a AXI Stream Data FIFO which is connected to a AXI DMA. AXI DMA is connected via the interconnect to the HP port. I am reading the data in the Data FIFO by connected its data_read line to my custom IP which just reads the data. The problem is that the amount of data transferred is not correct with every transaction. The traf_gen sends data in 16 data bursts, and whatever length I give in simple_dma_transfer() function, the data copied is always 16. I am not sure why is that.

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Might it be because your Zynq design only supports AXI3 and not AXI4?  The maximum AXI3 burst length is only 16 beats.

Which board are you using?

Also, this really belongs in the FPGA/embedded forum, not the microcontroller forum.


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