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Simple Design on Arty not working as expected - Simulation done


Question

I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me!

EDIT: I use the Arty board file and the xdc file provided by Digilent!


Code of the simple test gpio design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity io_test is
    generic(
            d_width		:	integer := 16;      --width of each data word
            size		:	integer := 64;      --number of data words the memory can store
            a_width     :   integer := 6       -- width of the adress bus 
            );
            
    port    (      
            i_clk       :   in      std_logic ;
            btn         : in        std_logic;
            led         : out       std_logic;
            led_2         : out       std_logic;
            test_io     : out     std_logic_vector ((d_width + a_width + 1) downto 0)
                              
            );

end io_test;

architecture Behavioral of io_test is
    signal clk_counter : integer := 0;
    signal clk_1hz : std_logic := '0';
    signal test_io_buf : std_logic_vector((d_width + a_width + 1) downto 0) := "000000000000000000000001";             
    signal insr  : std_logic_vector(2 downto 0);
    signal led_buf : std_logic := '0';
    
begin    
    btn_async : process(i_clk) begin
        if(rising_edge(i_clk)) then
           insr <= insr(1 downto 0) & btn;
        end if;     
    end process;
    
    io_test : process (i_clk) begin
        if(rising_edge(i_clk) and i_clk ='1') then
            if (insr(2 downto 1) = "01") then
                test_io_buf <= test_io_buf(d_width + a_width downto 0) & '0';
                led_buf <= not led_buf;
            end if;       
        end if;
               
    end process;
    
    test_io <= test_io_buf;
    led <= btn;
    led_2 <= led_buf;
    
end Behavioral;

If I simulate the file with:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all; 

entity test_of_ram is
end test_of_ram;

architecture Behavioral of test_of_ram is

component io_test

    port( 
            i_clk       :   in      std_logic ;
            btn         : in        std_logic;
            test_io     : out     std_logic_vector ((16 + 6 + 1) downto 0);
            led         : out   std_logic          
        );   
end component;
    ------------------------------------------------------------------------------
    -- Signals and Types
    ------------------------------------------------------------------------------
    constant OFFSET         : integer := 15;

    signal btn, clk    : std_logic := '1';
    signal led              : std_logic;
    signal test_io     : std_logic_vector ((16 + 6 + 1) downto 0);

begin
    dev_to_test: io_test 
    port map(
        btn => btn,
        test_io => test_io,
        i_clk => clk,
        led => led
    );
    
    ------------------------------------------------------------------------------
    -- Clock Stimulus
    ------------------------------------------------------------------------------
    clk_stim : process
    begin
           wait for 5 ns;
           clk <= not clk;
    end process ; -- clk_stim 
    
    
    ------------------------------------------------------------------------------
    -- IO Stimulus
    ------------------------------------------------------------------------------   
    io : process
    variable cnt: integer := 0;
    begin        
        for I in 1 to 16 loop  
            wait for 100ns; 
            btn <= not btn;
        end loop;
    end process ; -- read_write_stim   

end Behavioral;

I get the following result:

grafik.thumb.png.5e60524b11854c29d22005d991e6c019.png

Which is exactly what I want. But led_2 never lights up and only gpio0 stays on 3.3V (measured with multimeter)

xdc file:

## LEDs
set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports led]
set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports led_2 ]; #IO_25_35 Sch=led[5]
#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]

## Buttons
set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]

## Clock signal
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports i_clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]

## ChipKit Outer Digital Header
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {test_io[0]}]
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {test_io[1]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {test_io[2]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {test_io[3]}]
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {test_io[4]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {test_io[5]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {test_io[6]}]
set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { test_io[7]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {test_io[8]}]
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {test_io[9]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {test_io[10]}]
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {test_io[11]}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {test_io[12]}]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {test_io[13]}]
## ChipKit Inner Digital Header
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {test_io[14]}]
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {test_io[15]}]
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {test_io[16]}]
#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ram_addr[1] }]; #IO_25_14 		 			Sch=ck_io[29]
set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports {test_io[17]}]
set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {test_io[18]}]
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {test_io[19]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {test_io[20]}]
#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { test_io[21] }]; #IO_L15P_T2_DQS_RDWR_B_14 	Sch=ck_io[34]
#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { test_io[22] }]; #IO_L11N_T1_SRCC_14 			Sch=ck_io[35]
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports test_io[21]]
#set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {test_io[7]}]
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {test_io[22]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {test_io[23]}]
#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 		Sch=ck_io[40]
#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 			Sch=ck_io[41]

 

Edited by rddlr
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4 answers to this question

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Posted (edited)

I fixed this issue but nothing changes. Do you mind if it could be a timing problem?

If i delete "and i_clk ='1'" from the io_test process the design meet timings.

Can you help me to understand why?

Edited by rddlr
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Check the warnings. Most likely, there is one related to this construct:

>> if(rising_edge(i_clk) and i_clk ='1') then

the 2nd part is redundant (can't have a rising edge without the clock being high). But, FPGA-internally, information and clock signals are kept electrically separate (clocks drive edge-sensitive inputs, information signals drive level-sensitive inputs) and mixed only in exceptional use cases like ASIC emulation. In a nutshell, use clocks only in "rising_edge" constructs => "synchronous" design methodology.

Can you reduce the test case so it only shows the error and nothing else? Most likely, when that is done, you'll see the root cause for yourself.

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@rddlr,

It doesn't look like you've done anything to debounce those buttons.  Check out the diagrams here for example waveforms of what a single button press (or release) might look like without debouncing.  Indeed, some of those waveforms (not all) were even made with an Arty FPGA board.  Looking over your code, I don't see anything in what you've written that will take care of button bounces.  You might find this article gives the instruction you need to deal with them.  Both of them are part of a series I wrote some time ago on debouncing buttons.

Dan

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