FPGA and DAC Interface compatibility

[JKing]

Hello everyone！
Recently, I had a problem about  FPGA and DAC Interface compatibility . I have read many  material. But I still can not confirm.
I currently have the KC705  OR KCU105 FPGA board. 
I want to buy a DAC board AD9142A-M5375-EBZ or AD9122-M5375-EBZ with an adapter AD-DAC-FMC-ADP.
My question is, how can I find out if the DAC evaluation card with adapter board is compatible with the fpga board? Will the FPGA board support the DAC running with the maximum data rate ?
THANKS!

[Ana-Maria Balas]

Hello @JKing,

The system boards are from Xilinx, and the adapter board and DAC boards are from Analog Devices, so maybe you would find better responses on the Xilinx forum or Analog Devices, rather from our forum.

However, I asked one of our engineers about this issue and here is the response I got: 

For KC705 case with AD-DAC-FMC-ADP adapter and AD9142A-M5375-EBZ board compatibility between the pins from the DAC board, through the adapter board and up to the FPGA seems OK, for both FMC connectors on the KC705 board. Logical levels: The DAC uses LVDS, on the KC705 board the logical levels LVDS_25 must be set (they are the only ones available from the HR banks, where the FMC connectors are connected).

Maximum frequencies / maximum data rates at FPGA banks: in https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf on page 14, in Table 17, data rates for "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)", in the HR bank, for speed grades -2 (which is on the KC705 board), is 1250 Mb/s :

-The DAC can support a maximum of 575MHz on the DCI clock, with the data squared on opposite fronts (I and Q respectively, on opposite fronts of the clock) => 575Mb/s maximum useful data rate required by the DAC.

-Since we have to send the data to the DAC in quadrature, the maximum useful FPGA data rate is half of 1250 Mb/s, ie 625 Mb/s.

- 575Mb/s <625Mb/s, so it should be OK.

For security, you should look for a reference / example design with OSERDES for the respective board, modify it for your DAC and try to compile it with the desired frequencies, to see if the implementation passes.

-DATA_WIDTH = 4 to 14 at OSERDES does not affect us, because we actually receive the data of a word in parallel, on different LVDS pairs.

-If we were to use DAC in byte mode, then we would need 2 clock cycles to send 16 bits of I and 16 bits of Q. Of the 1250Mb/s that supports FPGA, we would remain with ¼, that is with 312.5 Mb/s, less than 575Mb/s, so I would not reach the maximum DAC rate.

Timing analysis: The FPGA must send the data synchronously with each edge of the DCI clock. Fortunately, the DAC has a DLL and a delay line respectively; Depending on the working frequency, one of the two can be used to ease the timing requirements (i.e. to apply a delay between the clock and the data, so that the timing of the DAC is satisfied).

You should analyze the rest of cases:

KCU105 with AD9142A-M5375-EBZ;

KC705 with AD9122-M5375-EBZ;

KCU105 with AD9122-M5375-EBZ.

Best regards.

Ana-Maria Balas

 

[JKing]

Hello Ana-Maria Balas

Thanks for your warm and careful reply.

Yes, I have asked the same question in ADI forum, but almost half a month has passed, nobody answered me .
Recently, I also have read some documents about kc705 and AD9142A carefully.So Yesterday, I bought the AD9142A-M5375-EBZ a little bit uncertainly, but now you confirmed me. Thanks!

Sincerely!

 

 

[Ana-Maria Balas]

Good luck with your project!