AXI4 FULL based block memory controller and Block memory gen

[Ram]

Hello guyz,  I I just want to know how AXI4 full utilize burst transfer of data. 

I mean suppose block memory generator have 4 register of 32 bit wide, and AXI bram controller have AXI4 full mode. 

In case of AXI lite we have 4 address 0to3 from writing data into block memory generator, but I when we use AXI4 full, then how much address we need 1 or it depends on some mechanics which also depends on board to board, actually problem is that, right now I don't have ZYBO board with me,  also emulator is also not installed in my system , so that's why I can't test my design. And its something called urgency.

I also want to add one more question. 

In one of design I found axi4 full bram controller generating 13 bit address, and then, by using address converter, it utilizing only 2 bits address of axi bram controller, from my opinion, why only 2 bits of address are taken into consideration, because we have only 4 register at block memory generator, so for avoiding warnings. He is using addresses converter, but the problem is when I look inside the address converter IP, he is utilizing bit 2 and 3 of axi bram controller, I mean suppose address[12:0] is coming through axi bram controller then he is taking address bits,  address [3:2] , It clearly looks that, this both the bits will  always be zero, because we want to access only 4 register, of block memory generator

suppose due to  axi4 full based bram controller, which can transfer whole data, (32 bit of 4) by utilizing burst transfers mechanism. only zero address is sufficient !!!

But again , at the block memory generator we need 4 different address for storing data into 4 different reg. 

and if all this my assumptions are true, then also i want know how in one cycle burst data transferred, and what is the meaning of address [3:2] of axi4 full bram controller (ultimately zero address or say only one address for all the four reg of block memory generator )

Truly, I say. I just  confused with this problem. 

I also attaching the screenshot. 

Please look over the pictures, help me out from this issue 

 

[Notarobot]

Hi, @Ram

Based the diagram you've allocated only 2 BRAM addresses for storing 32-bit data words. However based on your description you intended to have 4 memory cells. That is confusing to me as well.

Dual BRAM means that it can be read and written by two different actors using the same address area. For example, PL is writing data and PS is reading same data, asynchronously.

To my knowledge, if you use Vivado block diagram tools for 32-bit data you should have a variety of choices to configure the address width. Restrictions come when you choose nonstandard BRAM configurations. Unfortunately, documentation mostly relevant to pure HDL design. Block diagramming makes most of configuration for you, unless you want something exotic.

I am not sure I understand the need for the bt_shift module. In my projects the address is generated in the code polling /writing into BRAM. It seems to be simpler and clearer. BTW, in SDK BRAM address is located in the file xparameters.h, in VHDL it starts from 0.

Good luck!