I'm currently doing the '' write and read RAM'' project, in which I want to send characters to RAM through UART, and then read the data from the ram. I find two problems:
1.pin assignment of RAM. is there the pin number of ram in ARTY achematic, but it seems the pin number interfaced with other pin or isn't vaild.I show this problem in my slide in the attachment. for example, pin'C2' for reset also occurs in a pin of DDR3 in the achematic file.
2. the voltage required for RAM is around 1.5V, but it's 3.3V for other parts like clk or button. so when I set up my contraints, and some error occurs. I put the error
module uart_top(
input sys_clk, //system clk 100MHz
input sys_rst_n, //reset
//uart接口
input uart_rxd, //UART receive port
output uart_txd, //UART send port
input we,
input re,
input [2:0] addr,
input [7:0]wr_data
);
//parameter define
parameter CLK_FREQ = 100000000; //sys_clk
parameter UART_BPS = 115200; //bps
//wire define
wire uart_en_w; //UART_send_enable
wire [7:0] uart_data_w; //UART send data
wire clk_1m_w;
wire [7:0] mem_data;
//*****************************************************
//** main code
//*****************************************************
//串口接收模块 例化
uart_recv #( //parameter revalue
.CLK_FREQ (CLK_FREQ), //设置系统时钟频率
.UART_BPS (UART_BPS) //设置串口接收波特率
)
u_uart_recv( //串口接收模块
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.uart_rxd (uart_rxd),
.uart_done (uart_en_w),
.uart_data (uart_data_w)
);
//串口发送模块 例化
uart_send #( //parameter重新赋值
.CLK_FREQ (CLK_FREQ), //设置系统时钟频率
.UART_BPS (UART_BPS) //设置串口发送波特率
)
u_uart_send( //串口发送模块
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.uart_en (uart_en_w),
.uart_din (mem_data),
.uart_txd (uart_txd)
);
uart_ram #( //parameter重新赋值
.CLK_FREQ (CLK_FREQ), //设置系统时钟频率
.UART_BPS (UART_BPS) //设置串口接收波特率
)
u_uart_ram( //ram connect to uart
.clk (sys_clk),
.we (we),
.re (re),
.addr (addr),
.wr_data (uart_data_w),
.dout (mem_data)
);
endmodule
module uart_recv(
input sys_clk,
input sys_rst_n,
input uart_rxd,
output reg uart_done, //接收一帧数据完成标志信号
output reg [7:0] uart_data //接收的数据
);
//parameter define
parameter CLK_FREQ = 100000000; //系统时钟频率 50M
parameter UART_BPS = 115200; //串口波特率
localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率,
//需要对系统时钟计数BPS_CNT次
//reg define
reg uart_rxd_d0;
reg uart_rxd_d1;
reg [15:0] clk_cnt;
reg [ 3:0] rx_cnt;
reg rx_flag;
reg [ 7:0] rxdata;
//wire define
wire start_flag;
//*****************************************************
//** main code
//*****************************************************
//*************************************************************************************************
assign start_flag = uart_rxd_d1 & (~uart_rxd_d0);
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
uart_rxd_d0 <= 1'b0;
uart_rxd_d1 <= 1'b0;
end
else begin
uart_rxd_d0 <= uart_rxd;
uart_rxd_d1 <= uart_rxd_d0;
end
end
//************************************************************************************************
//*****************************************************************************************************
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
rx_flag <= 1'b0;
else begin
if(start_flag)
rx_flag <= 1'b1;
else if((rx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2))
rx_flag <= 1'b0;
else
rx_flag <= rx_flag;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
clk_cnt <= 16'd0;
rx_cnt <= 4'd0;
end
else if ( rx_flag ) begin
if (clk_cnt < BPS_CNT - 1) begin
clk_cnt <= clk_cnt + 1'b1;
rx_cnt <= rx_cnt;
end
else begin
clk_cnt <= 16'd0;
rx_cnt <= rx_cnt + 1'b1;
end
end
else begin
clk_cnt <= 16'd0;
rx_cnt <= 4'd0;
end
end
//*****************************************************************************************************
always @(posedge sys_clk or negedge sys_rst_n) begin
if ( !sys_rst_n)
rxdata <= 8'd0;
else if(rx_flag)
if (clk_cnt == BPS_CNT/2) begin
case ( rx_cnt )
4'd1 : rxdata[0] <= uart_rxd_d1;
4'd2 : rxdata[1] <= uart_rxd_d1;
4'd3 : rxdata[2] <= uart_rxd_d1;
4'd4 : rxdata[3] <= uart_rxd_d1;
4'd5 : rxdata[4] <= uart_rxd_d1;
4'd6 : rxdata[5] <= uart_rxd_d1;
4'd7 : rxdata[6] <= uart_rxd_d1;
4'd8 : rxdata[7] <= uart_rxd_d1;
default:;
endcase
end
else
rxdata <= rxdata;
else
rxdata <= 8'd0;
end
//
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
uart_data <= 8'd0;
uart_done <= 1'b0;
end
else if(rx_cnt == 4'd9) begin
uart_data <= rxdata;
uart_done <= 1'b1; //并将接收完成标志位拉高
end
else begin
uart_data <= 8'd0;
uart_done <= 1'b0;
end
end
endmodule
module uart_ram(//clk,we,re,addr,dout,wr_data
input clk,
input we,
input re,
input [2:0] addr,
output reg [7:0] dout,
input [7:0]wr_data
);
parameter ADD_WIDTH=3;
parameter DATA_WIDTH=8;
/*input clk;
input we;
input re;
input [2:0] addr;
output reg [7:0] dout;
input [7:0]wr_data;*/
//output reg [7:0] mod;
parameter CLK_FREQ = 100000000; //system clock
parameter UART_BPS = 115200; //port bps
localparam BPS_CNT = CLK_FREQ/UART_BPS; //BPS_CNT
reg[DATA_WIDTH-1:0] mem [2**ADD_WIDTH-1:0];
always@(posedge clk)
begin
if (we)
begin
mem[addr]<=wr_data;
end
end
always@(posedge clk)
begin
if (re && !we)
begin
dout= mem[addr];
// mod= dout[7:0];
end
else
begin
dout=8'd0;
//mod=8'd0;
end
end
endmodule
module uart_send(
input sys_clk, //系统时钟
input sys_rst_n, //系统复位,低电平有效
input uart_en, //发送使能信号
input [7:0] uart_din, //待发送数据
output reg uart_txd //UART发送端口
);
//parameter define
parameter CLK_FREQ = 100000000; //系统时钟频率
parameter UART_BPS = 115200; //串口波特率
localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率,对系统时钟计数BPS_CNT次
//reg define
reg uart_en_d0;
reg uart_en_d1;
reg [15:0] clk_cnt;
reg [ 3:0] tx_cnt;
reg tx_flag;
reg [ 7:0] tx_data;
//wire define
wire en_flag;
//*****************************************************
//** main code
assign en_flag = (~uart_en_d1) & uart_en_d0;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
uart_en_d0 <= 1'b0;
uart_en_d1 <= 1'b0;
end
else begin
uart_en_d0 <= uart_en;
uart_en_d1 <= uart_en_d0;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
tx_flag <= 1'b0;
tx_data <= 8'd0;
end
else if (en_flag) begin
tx_flag <= 1'b1;
tx_data <= uart_din;
end
else
if ((tx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2))
begin
tx_flag <= 1'b0;
tx_data <= 8'd0;
end
else begin
tx_flag <= tx_flag;
tx_data <= tx_data;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
clk_cnt <= 16'd0;
tx_cnt <= 4'd0;
end
else if (tx_flag) begin
if (clk_cnt < BPS_CNT - 1) begin
clk_cnt <= clk_cnt + 1'b1;
tx_cnt <= tx_cnt;
end
else begin
clk_cnt <= 16'd0;
tx_cnt <= tx_cnt + 1'b1;
end
end
else begin //发送过程结束
clk_cnt <= 16'd0;
tx_cnt <= 4'd0;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
uart_txd <= 1'b1;
else if (tx_flag)
case(tx_cnt)
4'd0: uart_txd <= 1'b0;
4'd1: uart_txd <= tx_data[0];
4'd2: uart_txd <= tx_data[1];
4'd3: uart_txd <= tx_data[2];
4'd4: uart_txd <= tx_data[3];
4'd5: uart_txd <= tx_data[4];
4'd6: uart_txd <= tx_data[5];
4'd7: uart_txd <= tx_data[6];
4'd8: uart_txd <= tx_data[7];
4'd9: uart_txd <= 1'b1;
default: ;
endcase
else
uart_txd <= 1'b1;
end
endmodule
Question
weilai
Hi, guys:
I'm currently doing the '' write and read RAM'' project, in which I want to send characters to RAM through UART, and then read the data from the ram. I find two problems:
1.pin assignment of RAM. is there the pin number of ram in ARTY achematic, but it seems the pin number interfaced with other pin or isn't vaild.I show this problem in my slide in the attachment. for example, pin'C2' for reset also occurs in a pin of DDR3 in the achematic file.
2. the voltage required for RAM is around 1.5V, but it's 3.3V for other parts like clk or button. so when I set up my contraints, and some error occurs. I put the error
module uart_top( input sys_clk, //system clk 100MHz input sys_rst_n, //reset //uart接口 input uart_rxd, //UART receive port output uart_txd, //UART send port input we, input re, input [2:0] addr, input [7:0]wr_data ); //parameter define parameter CLK_FREQ = 100000000; //sys_clk parameter UART_BPS = 115200; //bps //wire define wire uart_en_w; //UART_send_enable wire [7:0] uart_data_w; //UART send data wire clk_1m_w; wire [7:0] mem_data; //***************************************************** //** main code //***************************************************** //串口接收模块 例化 uart_recv #( //parameter revalue .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口接收波特率 ) u_uart_recv( //串口接收模块 .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .uart_rxd (uart_rxd), .uart_done (uart_en_w), .uart_data (uart_data_w) ); //串口发送模块 例化 uart_send #( //parameter重新赋值 .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口发送波特率 ) u_uart_send( //串口发送模块 .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .uart_en (uart_en_w), .uart_din (mem_data), .uart_txd (uart_txd) ); uart_ram #( //parameter重新赋值 .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口接收波特率 ) u_uart_ram( //ram connect to uart .clk (sys_clk), .we (we), .re (re), .addr (addr), .wr_data (uart_data_w), .dout (mem_data) ); endmodule module uart_recv( input sys_clk, input sys_rst_n, input uart_rxd, output reg uart_done, //接收一帧数据完成标志信号 output reg [7:0] uart_data //接收的数据 ); //parameter define parameter CLK_FREQ = 100000000; //系统时钟频率 50M parameter UART_BPS = 115200; //串口波特率 localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率, //需要对系统时钟计数BPS_CNT次 //reg define reg uart_rxd_d0; reg uart_rxd_d1; reg [15:0] clk_cnt; reg [ 3:0] rx_cnt; reg rx_flag; reg [ 7:0] rxdata; //wire define wire start_flag; //***************************************************** //** main code //***************************************************** //************************************************************************************************* assign start_flag = uart_rxd_d1 & (~uart_rxd_d0); always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_rxd_d0 <= 1'b0; uart_rxd_d1 <= 1'b0; end else begin uart_rxd_d0 <= uart_rxd; uart_rxd_d1 <= uart_rxd_d0; end end //************************************************************************************************ //***************************************************************************************************** always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) rx_flag <= 1'b0; else begin if(start_flag) rx_flag <= 1'b1; else if((rx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) rx_flag <= 1'b0; else rx_flag <= rx_flag; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin clk_cnt <= 16'd0; rx_cnt <= 4'd0; end else if ( rx_flag ) begin if (clk_cnt < BPS_CNT - 1) begin clk_cnt <= clk_cnt + 1'b1; rx_cnt <= rx_cnt; end else begin clk_cnt <= 16'd0; rx_cnt <= rx_cnt + 1'b1; end end else begin clk_cnt <= 16'd0; rx_cnt <= 4'd0; end end //***************************************************************************************************** always @(posedge sys_clk or negedge sys_rst_n) begin if ( !sys_rst_n) rxdata <= 8'd0; else if(rx_flag) if (clk_cnt == BPS_CNT/2) begin case ( rx_cnt ) 4'd1 : rxdata[0] <= uart_rxd_d1; 4'd2 : rxdata[1] <= uart_rxd_d1; 4'd3 : rxdata[2] <= uart_rxd_d1; 4'd4 : rxdata[3] <= uart_rxd_d1; 4'd5 : rxdata[4] <= uart_rxd_d1; 4'd6 : rxdata[5] <= uart_rxd_d1; 4'd7 : rxdata[6] <= uart_rxd_d1; 4'd8 : rxdata[7] <= uart_rxd_d1; default:; endcase end else rxdata <= rxdata; else rxdata <= 8'd0; end // always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_data <= 8'd0; uart_done <= 1'b0; end else if(rx_cnt == 4'd9) begin uart_data <= rxdata; uart_done <= 1'b1; //并将接收完成标志位拉高 end else begin uart_data <= 8'd0; uart_done <= 1'b0; end end endmodule module uart_ram(//clk,we,re,addr,dout,wr_data input clk, input we, input re, input [2:0] addr, output reg [7:0] dout, input [7:0]wr_data ); parameter ADD_WIDTH=3; parameter DATA_WIDTH=8; /*input clk; input we; input re; input [2:0] addr; output reg [7:0] dout; input [7:0]wr_data;*/ //output reg [7:0] mod; parameter CLK_FREQ = 100000000; //system clock parameter UART_BPS = 115200; //port bps localparam BPS_CNT = CLK_FREQ/UART_BPS; //BPS_CNT reg[DATA_WIDTH-1:0] mem [2**ADD_WIDTH-1:0]; always@(posedge clk) begin if (we) begin mem[addr]<=wr_data; end end always@(posedge clk) begin if (re && !we) begin dout= mem[addr]; // mod= dout[7:0]; end else begin dout=8'd0; //mod=8'd0; end end endmodule module uart_send( input sys_clk, //系统时钟 input sys_rst_n, //系统复位,低电平有效 input uart_en, //发送使能信号 input [7:0] uart_din, //待发送数据 output reg uart_txd //UART发送端口 ); //parameter define parameter CLK_FREQ = 100000000; //系统时钟频率 parameter UART_BPS = 115200; //串口波特率 localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率,对系统时钟计数BPS_CNT次 //reg define reg uart_en_d0; reg uart_en_d1; reg [15:0] clk_cnt; reg [ 3:0] tx_cnt; reg tx_flag; reg [ 7:0] tx_data; //wire define wire en_flag; //***************************************************** //** main code assign en_flag = (~uart_en_d1) & uart_en_d0; always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_en_d0 <= 1'b0; uart_en_d1 <= 1'b0; end else begin uart_en_d0 <= uart_en; uart_en_d1 <= uart_en_d0; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin tx_flag <= 1'b0; tx_data <= 8'd0; end else if (en_flag) begin tx_flag <= 1'b1; tx_data <= uart_din; end else if ((tx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) begin tx_flag <= 1'b0; tx_data <= 8'd0; end else begin tx_flag <= tx_flag; tx_data <= tx_data; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin clk_cnt <= 16'd0; tx_cnt <= 4'd0; end else if (tx_flag) begin if (clk_cnt < BPS_CNT - 1) begin clk_cnt <= clk_cnt + 1'b1; tx_cnt <= tx_cnt; end else begin clk_cnt <= 16'd0; tx_cnt <= tx_cnt + 1'b1; end end else begin //发送过程结束 clk_cnt <= 16'd0; tx_cnt <= 4'd0; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) uart_txd <= 1'b1; else if (tx_flag) case(tx_cnt) 4'd0: uart_txd <= 1'b0; 4'd1: uart_txd <= tx_data[0]; 4'd2: uart_txd <= tx_data[1]; 4'd3: uart_txd <= tx_data[2]; 4'd4: uart_txd <= tx_data[3]; 4'd5: uart_txd <= tx_data[4]; 4'd6: uart_txd <= tx_data[5]; 4'd7: uart_txd <= tx_data[6]; 4'd8: uart_txd <= tx_data[7]; 4'd9: uart_txd <= 1'b1; default: ; endcase else uart_txd <= 1'b1; end endmodule
massage in the attachment too.
1.pptx error massage.txt
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