FMC pcam adapter with ultrascale+

[galhtc]

Hey,

I'm using the VCU118 evaluation board with the Xilinx Ultrascale+ XCVU9P. I'm trying to connect to the FMC-pcam-adapter card. 

The MC20901 offers a SLVS to LVDS Conversion, so I can connect to the FPGA with LVDS and LVCMOS IO-STANDARDS.

I also have a CSI controller with a PPI interface. But, the Vivado's D-PHY IP can't have the HS(high-speed) and LP(lower-power) "split" into two differential pairs. 

Is there a way to use the Xilinx's D-PHY IP for ultrascale with the board ? or find a simple verilog connverter or DPHY ? 

Thanks,

-Gal 

[elodg]

Two issues:

The pinout of the FMC Pcam Adapter might not support more than one Pcam when combined with an UltraScale FPGA: https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual#fpga_io_architecture_compatibility. We are designing a new version of the adapter that improves UltraScale compatibility.

Secondly, Xilinx D-PHY IP expects D-PHY I/O standard for UltraScale+ architecture, not the split LVDS & LVCMOS that the adapter provides. One needs to modify the source code of the IP or edit the netlist to modify the input buffers. We are investigating this for the new version of the adapter and will provide more details here. Pinging @BogdanVanca.

[elodg]

Attaching an example tcl script that edits the netlist for selected ports replacing the D-PHY buffer with IBUFDS and IBUF buffers. Edit the port names in the script to suit your project and add it as a constraint file to the project with the following properties:

set_property used_in implementation [get_files post_synth_dhpy_lvds.tcl]
set_property used_in_simulation 0 [get_files post_synth_dhpy_lvds.tcl]
set_property used_in_synthesis 0 [get_files post_synth_dhpy_lvds.tcl]
set_property PROCESSING_ORDER EARLY [get_files post_synth_dhpy_lvds.tcl]

This makes sure the tcl is considered only after synthesis and before the other xdc files. New ports will be created (low-power nets), so constrain those in an xdc.

We will publish a fully functional project for the Genesys ZU, eventually.

post_synth_dhpy_lvds.tcl

[elizegi]

Hi,

Is there an approximate date for the new version of the adapter for UltraScale+ devices?

[elodg]

Q2 2020

[elizegi]

Great! Thanks for the good news.

Is there a way to make a preorder the adapter, directly from Digilent or from a distributor? I'm very interested in it and would like to have it in my hands as soon as possible...

[elodg]

No pre-order yet, keep checking our website for updates or sign-up to our newsletter.

[manboy]

Is there any update of the new adapter for ultra-scale+ ?

 

Thanks.

[elodg]

The prototypes have been verified, and we got entangled in support for 2020.1. Sorry, I do not have a better timeline.

[binjon178]

Any new version update ?

Thanks,

- Robert